Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-08-31T07:02:08Z | - |
dc.date.available | 2021-08-31T07:02:08Z | - |
dc.date.issued | 2020-08 | - |
dc.identifier.citation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 20, no. 4, page. 390-404 | en_US |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE09417472 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/164728 | - |
dc.description.abstract | With advancements in process technology and ever-increasing complexity of digital circuits, testing has become a prominent problem. The lengthy scan chains used for testing semiconductor chips cause not only the longer test time but also excessive test power consumption. Such excessive test power (especially peak power during shifting) can cause reliability degradation for the semiconductor. To resolve this problem, we introduce an exclusive shiftin and shift-out method along with a scan chain reordering algorithm. The proposed method is evaluated with several benchmark circuits including ISCAS'89, ITC'99 and IWLS'05. The results indicate that the proposed technique reduces the average power and helps mitigating the peak power consumption. In addition, an optimization method is introduced to reduce the area overhead of proposed scan technique. As a result, area overhead of proposed scan architecture was reduced to 1-11%. | en_US |
dc.description.sponsorship | This work was supported in part by the National Research Foundation of Korea Grant through the Ministry of Education, Science and Technology under Grant (NRF-2017R1D1A1B03030821), in part by the Ministry of Trade, Industry and Energy under Grant (10052875), and in part by the Korea Semiconductor Research Consortium support program for the development of future semiconductor device. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEK PUBLICATION CENTER | en_US |
dc.subject | Design-for-testability (DFT) | en_US |
dc.subject | shift power reduction | en_US |
dc.subject | low power testing | en_US |
dc.subject | scan chain reordering | en_US |
dc.title | Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering | en_US |
dc.type | Article | en_US |
dc.relation.no | 4 | - |
dc.relation.volume | 20 | - |
dc.identifier.doi | 10.5573/JSTS.2020.20.4.390 | - |
dc.relation.page | 390-404 | - |
dc.relation.journal | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.contributor.googleauthor | Kim, Dooyoung | - |
dc.contributor.googleauthor | Kim, Jinuk | - |
dc.contributor.googleauthor | Ibtesam, Muhammad | - |
dc.contributor.googleauthor | Solangi, Umair Saeed | - |
dc.contributor.googleauthor | Park, Sungju | - |
dc.relation.code | 2020051601 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.