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An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs

Title
An area and power efficient interpolation scheme using variable current control for 10-bit data drivers in mobile active-matrix LCDs
Author
이병훈
Keywords
Buffer amplifier; data driver; digital-to-analog converter (DAC); interpolation; LCD; piecewise linear; variable current control (VCC)
Issue Date
2019-05
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v. 65, no. 2, page. 253-262
Abstract
This paper presents an area and power efficient interpolation scheme using variable current control (VCC) for 10-bit data drivers in mobile active-matrix LCDs. The VCC interpolation can be embedded in buffer amplifiers as sub-digital-to-analog converters (DACs), reducing the DAC area without requiring additional power and conversion time. Moreover, interpolation errors due to transistor nonlinearity can be compensated through delicate current ratio control, optimizing both accuracy and area efficiency of the high-resolution data driver. The prototype 10-bit data driver with a 6-bit resistor DAC and a 4-bit interpolation sub-DAC occupies the chip area of 460 mu m x 14 mu m per channel, which is 10.7% smaller than the conventional 8bit data driver. The data driver consumes static current of 1 mu A/channel without dissipating additional power for interpolation. The measured integral nonlinearity and differential nonlinearity are 0.4 LSB and 0.7 LSB, respectively. The proposed scheme has competitive performance in terms of driving accuracy, chip size shrinkage, and static power consumption for high-resolution data drivers.
URI
https://ieeexplore.ieee.org/document/8648213https://repository.hanyang.ac.kr/handle/20.500.11754/160717
ISSN
0098-3063; 1558-4127
DOI
10.1109/TCE.2019.2900512
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRICAL AND BIOMEDICAL ENGINEERING(전기·생체공학부) > Articles
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