자가보정을 위한 Tunable Split SAR 구조의 아날로그-디지털 컨버터

Abstract

Successive-approximation-resister(SAR) analog-to-digital converter (ADC)의 칩 공정과정으로부터 발생되는 다양한 defect들 중 capacitor mismatch는 SAR ADC의 심각한 성능저하를 발생시켜 yield를 감소시킨다. SAR ADC의 성능을 결정짓는 capacitive digital-to-analog converter (CDAC)에서 capacitor mismatch가 발생하여 SAC ADC의 linearity를 저하시키게 된다. 본 논문에서는 capacitor mismatch를 완화시켜 SAR ADC의 linearity를 향상시키는 효과적인 background self-calibration(자가보정) 기술을 제안한다. Split구조기반의 SAR ADC내에서 CDAC의 capacitance들은 variable capacitor(i.e., metal-oxide-semiconductor capacitor(MOSCAP))로 설계된다. 이들의 capacitance들을 직접 측정하지 않고, capacitor array의 연결을 여러 조합으로 만들어 capacitor들간의 비율을 알아내고, 이 data를 이용하여 보정이 필요한 capacitor들의 body voltage를 update한다. 본 논문에서 제안하는 background 자가보정 기술의 성능을 검증하기 위해, behavioral model의 MOSCAP을 기반으로 하는 8-bit split SAR ADC를 구현하여 시뮬레이션 하였다. 시뮬레이션 결과로서, SNR과 THD가 각각 41.756 dB, 36.854 dB에서 48.567 dB, 77.349 dB로 증가하였으며, nonideality 실험을 통해 다양한 크기의 capacitor mismatch에 대한 SNR, THD, 보정된 capacitance 값의 높은 안정성을 보였다.; The capacitor mismatch issue in diverse defects from the manufacturing process significantly affects the performance of the successive-approximation-resister (SAR) analog-to-digital converter (ADC), resulting in yield loss. The capacitor mismatch is incurred in the capacitive array of the capacitive digital-to-analog converter (CDAC), which determines the overall performance of the SAR ADC, thereby reducing the ADC linearity. In this thesis, an effective background self-calibration technology, which improves the linearity of SAR ADC by mitigating the capacitor mismatch, is proposed. The capacitor-array of the CDAC in the SAR ADC based on the split architecture is designed using variable capacitors, i.e., metal-oxide-semiconductor capacitors (MOSCAP). Various connections among capacitors are made to measure the ratio between capacitors, and to update their body voltage of a MOSCAP under calibration in order to correct their capacitances, and thus the proposed method does not require the capacitance measurement performed in conventional method. The behavioral simulation is conducted by modeling the 8-bit split SAR ADC with the MOSCAP, in order to evaluate the proposed background self-calibration technology. The simulation results show that the signal-to-noise ratio (SNR) and total-harmonic-distortion (THD) are enhanced from 41.756 dB to 48.567 dB, and 36.854 dB to 77.349 dB, respectively. In addition, the values of SNR, THD and calibrated capacitances with respect to diverse capacitor mismatches are shown for the nonideality.