Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-02-02T07:35:50Z | - |
dc.date.available | 2021-02-02T07:35:50Z | - |
dc.date.issued | 2002-11 | - |
dc.identifier.citation | Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)., page. 344-349 | en_US |
dc.identifier.isbn | 0-7695-1825-7 | - |
dc.identifier.isbn | 978-0-7695-1825-1 | - |
dc.identifier.issn | 1081-7735 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/1181735?arnumber=1181735&SID=EBSCO:edseee | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/157786 | - |
dc.description.abstract | For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations. | en_US |
dc.description.sponsorship | Research supported by KOSEF 2000-1-30200-002-3 | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.title | A Simple Wrapped Core Linking Module for SoC Test Access | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ATS.2002.1181735 | - |
dc.contributor.googleauthor | Song, Jaehoon | - |
dc.contributor.googleauthor | Park, Sungju | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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