Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2020-11-09T05:09:49Z | - |
dc.date.available | 2020-11-09T05:09:49Z | - |
dc.date.issued | 2003-03 | - |
dc.identifier.citation | 전기학회논문지 D. v. 52, no. 3, page. 156-162 | en_US |
dc.identifier.issn | 1229-6287 | - |
dc.identifier.uri | http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01261997 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/155250 | - |
dc.description.abstract | For a Systern—on-a—Ch ip(SoC ) comprised of mu ltip le IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based W rapped Core L ink ing M odu le (W C LM ) tha t enables systematic integration of IE E E 1149.1 T A P 'd cores and P I 500 wrapped cores w ith requiring least amount o f area overhead compared w ith other state—o f—art techniques. The design preserves compatibility w ith standards and scalability for hierarchical access | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 대한전기학회 | en_US |
dc.subject | 경계스캔 설계 | en_US |
dc.subject | IEEE 1149.1 | en_US |
dc.subject | P1500 | en_US |
dc.subject | SoC 테스트 | en_US |
dc.subject | 코아 테스트 | en_US |
dc.title | 계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계 | en_US |
dc.title.alternative | A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access | en_US |
dc.type | Article | en_US |
dc.relation.journal | 전기학회논문지(A,B,C,D) | - |
dc.contributor.googleauthor | 이현빈 | - |
dc.contributor.googleauthor | 박성주 | - |
dc.relation.code | 2012101073 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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