Design and Implementation of Hardware Accelerator with Runtime Configurable Parameters for Lossless Data Compression

Abstract

Studies related to data compression are being conducted to cope with the increase of storage and transmission cost caused by growth of the amount of digital data. In addition, several studies have been conducted to perform compression using a hardware-based acceleration technique to reduce the computation overhead due to compression and to obtain performance improvement. Most of conventional compression accelerators focused on improving performance through parallelization or pipelining. However, these studies still have room for improvement in terms of analyzing the operation of the compression and considering the characteristics of the compression algorithm. This dissertation proposes a hardware architecture of compression accelerator and its design methods. The hardware architecture proposed in this dissertation targets the LZ77 algorithm, which consumes a long time, among the components of zlib, a widely used software compression library. The proposed architecture is designed considering the two aspects mentioned above. First, this dissertation presents the prototype of compression accelerator architecture and its operation analysis. The study revealed that some of the operations performed on compression accelerators, in fact, do not need to be performed. In the first study, it was found that detecting unnecessary operations and preventing these operations from being performed reduce the hardware resource usage of the accelerator prototype and contribute to performance improvement. Next, this dissertation presents a design method of compression acceleration hardware that can adjust the compression ratio and throughput at runtime. Previously proposed compression accelerators have difficulty in adjusting the priority of two factors at runtime, which may limit the performance improvement of the system. Based on the prototype suggested in the first study, the proposed accelerator architecture is designed to be able to adjust the compression ratio and throughput at runtime. The proposed architecture has several operation modes and adjusts these two factors by changing the degree of parallelism of the internal operation for each mode. In addition, this study found that the unnecessary operations described above limit the possibility of increasing compression ratio and throughput in each mode. Through experiments, it was confirmed that preventing unnecessary operation from being performed increases the throughput and compression ratio of each mode. Through the two studies in the dissertation, the proposed compression accelerator provides high throughput while securing the runtime configurability of compression ratio and throughput. It was confirmed that the proposed architecture is meaningful as a compression accelerator through comparison with the previously proposed accelerators. In addition, the study shows the feasibility of applying the trade-off-based compression technique with using proposed accelerator.