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GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data Parallel Architectures

Title
GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data Parallel Architectures
Author
박영준
Issue Date
2019-06
Publisher
Association for Computing Machinery
Citation
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019, Page. 1-6
Abstract
Although approximate computing is widely used, it requires substantial programming effort to find appropriate approximation patterns among multiple pre-defined patterns to achieve a high performance. Therefore, we propose an automatic approximation framework called GATE to uncover hidden opportunities from any data-parallel program regardless of the code pattern or application characteristics using two compiler techniques, namely subgraph-level approximation (SGLA) and approximate thread merge(ATM). GATE also features conservative/aggressive tuning and dynamic calibration to maximize the performance while maintaining the TOQ level during runtime. Our framework achieves an average performance gain of 2.54x over the baseline with minimum accuracy loss.
URI
https://dl.acm.org/doi/10.1145/3316781.3317833https://repository.hanyang.ac.kr/handle/20.500.11754/151854
ISBN
9781450367257
ISSN
0738-100X
DOI
10.1145/3316781.3317833
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE(컴퓨터소프트웨어학부) > Articles
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