A LOW-NOISE CMOS MIXER USING SWITCHED BIASING TECHNIQUE AND A SINGLE-SIDE BAND MIXER FOR ULTRA-WIDEBAND SYSTEMS

Abstract

In this thesis, a low-noise CMOS mixer using switched biasing technique and a single-sideband mixer for ultra-wideband (UWB) systems are presented. A low-noise CMOS mixer using switched biasing technique in 0.13-μm RF CMOS process is proposed. The proposed mixer employs three techniques; First, a current source using switched biasing with two transistors is adopted to reduce flicker noise of the tail transistor by operating it between strong inversion and accumulation region. Second, an internal inductor, LP, is added to cancel effects of parasitic capacitances between source nodes of the LO stage. Finally, a load stage is designed with two PMOS transistors and resistors. PMOS transistors are generally affected by less flicker noise than NMOS transistors. Direct and indirect noise sources are reduced by using switched-biasing, internal inductor, and load stage with PMOS transistors and resistors. Calculated results show a conversion gain of 2 - 14.3 dB and a DSB noise figure of 8.43 - 14 dB in overall UWB band. In addition, the mixer performs IIP3 of -3 dBm with a power dissipation of 5.57 mW from 1.2-V supply. The chip occupies 0.72 mm × 0.72 mm. A single-side band (SSB) mixer presents for a fast-hopping frequency synthesizer that generates clocks for the seven bands distributed from 3 to 9.5 GHz with a switching time of less than 1 ns. A load of the SSB mixer is implemented as a LC-tank band-pass filter. The resonance frequency of the LC-tank load can be controlled the capacitor bank switch by digitally. Fabricated in 0.13-㎛ CMOS technology, this work achieves the harmonic suppressions of -38 and -21 dBc over 3.432 to 9.24 GHz.