A Signal Integrity Verification Method for On-Chip Coplanar Interconnect Structure

Abstract

This Thesis presents a general guideline for the selection between coplanar Ground-Signal-Ground(GSG) and Power-Signal-Ground(PSG) structures as shielding systems for critical on-chip global interconnect lines (such as clock and data bus) on the basis of thorough analysis and comparison. For correct analysis of a rather complex PSG structure, a per unit length (PUL) parameter extraction technique is proposed. Based on the analysis it is shown that at lower data rates (< 5 Gbps), arbitrary selection of GSG or PSG (with single or multi signal lines in between the shielding structures) may work as their performance does not differ much (although the later offers an advantage of area over head mitigation, caused by the former). At higher data rates (> 5 Gbps), on the other hand, with one signal line, Power/Ground shielding structure is shown to be of advantage performance wise (in addition to being area efficient). But with multi signal lines, the cross talk effect in Power/Ground structure is more pronounced as compared to its GS..SG counterpart, which offers better performance. In addition, the phenomenon of reference plane exchange in a four layered stack up is explained using the proposed coplanar analysis technique. It is shown that at lower bit rates (< 5 Gbps), the phenomenon has minimum effect on signal integrity. But as the data rate increases, the phenomenon adversely affects the signal quality.