Direct-conversion RF Receiver for 5GHz Wireless LAN in CMOS Technology

Abstract

This thesis describes a CMOS direct-conversion receiver for 5GHz wireless LAN. Sub-harmonic mixing is used for down-conversion to minimize the DC-offset due to LO-leakage. The residual DC-offset is cancelled by a digital-to-analog converter at the output of mixer. All the signal paths are fully differential to minimize noise coupling and even-order harmonic distortion. The channel-selection filtering is performed by a fifth-order Chebyshev active-RC filter which is followed by a programmable gain amplifier (PGA). For quadrature down-conversion with sub-harmonic mixing, octa-phase LO signals are generated by an integer-N type frequency synthesizer. And also, a multi-phase shifting network with third-order RC-CR filter and active interpolator is described. Implemented in a 0.18??m CMOS technology, the receiver dissipates 97mA from a 1.8V supply voltage and has 6.5dB noise figure (NF) and -4dBm input third-order intercept point (iIP3). The phase noise of the closed-loop voltage controlled oscillator (VCO) is -108dBc/Hz at 1MHz offset. The phase accuracy of the multi-phase shifting network is measured to be better than 0.8?X. The amplitude mismatch among the multi-phase outputs is smaller than 0.4% over the frequency range of 2.0-3.0 GHz of the half of the RF frequency.