Charge trap 플래시 기억소자에서 인접 셀의 포획 영역 사이의 전기적 간섭 성질에 대한 연구
- Charge trap 플래시 기억소자에서 인접 셀의 포획 영역 사이의 전기적 간섭 성질에 대한 연구
- Other Titles
- A study on electrical interference properties between trap layers of neighboring cells in the charge trap flash memory devices
- Alternative Author(s)
- Jang, Sang Hyun
- Issue Date
- NAND flash memories have been particularly interesting due to their promising applications in mass storage electronic devices, which offer advantages of high-density storage and low cost. The prospect of potential applications of NAND flash memories in portable mass data storage applications has led to substantial research and development efforts to increase the memory storage capacibility and to enhance operating speed. The Tantalium oxide-Aluminium oxide-silicon nitride-Silicon oxide-silicon (TANOS) type flash memory devices have been very attractive because of the interest in their promising applications in high-density and low-power flash memory devices. However, because the scaling down process of the conventional TANOS type flash memory technology encountered with the difficult technical challenges and device performance limitations, various methods were used to overcome the scaling-down limits of the conventional TANOS type flash memories. The multilevel cell (MLC) techniques is a one of the method to overcome the scaling-down limits. The MLC techniques, in which multi-bits are stored in a single floating gate memory cell, have been particularly interesting due to a dramatic increase in the storage capacity. But as cell transistor sizes are scaled down, it is a critical concern to obtain a tight threshold voltage (VTH) distribution in MLC NAND Flash memory. The biggest problems in MLC operation below the sub-40-nm node region is the cell-to-cell interference, detrimentally widening cell VTH distribution in MLC arrays.
The simulation results showed cell-to-cell interference is biggest problem below the sub-20 nm at the TANOS type flash memory device. So recess field was proposed. Cell-to-cell interference decrease when structure has the small VEFH value. And recess field also change the device operation property. Recess field and word line wrap the trap region, the area of voltage active region are increased. For this reason capacitance at gate region increase so that coupling ratio increases in the TANOS type flash memory device. For this reason when the structure has small VEFH value, the trap region is applied high voltage and the number of trapped charges is increased in the trap layer. And in reading operation, when the structure has small value of VEFH, the device has high level on current and good switching property. But the GIDL also increases. For this reason structure of TANOS type flash device was decided optimum VEFH value.
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- GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Master)
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