A Single-Ended Receiver Using Self-Reference Generation Technique for DRAM Interface

Abstract

Over the years, there has been growing demand for increasing the data processing capability of computer systems. Accordingly, many chip designers have focused on developing inter-chip communication techniques that offer higher bandwidths at low costs. In this sense, designing the DRAM interface and finding a cost-effective means to increase the data rate between memory controller and memories have become major challenges. DRAM interfaces typically use the multi-drop single-ended architecture to reduce the number of pins and the area. However, in the multi-drop topology, signal integrity issues such as inter-symbol interference (ISI), linear ISI, caused by the input-pin loading of DRAM chips as well as reflection, nonlinear ISI, at stub, make it difficult to achieve higher bandwidth. Moreover, the single-ended receiver is susceptible to reference voltage noise. Thus, it is essential to overcome ISI and optimize the reference voltage to increase the data rate. In this thesis, a 3.2Gbps single-ended receiver using the self-reference generation technique for DRAM interfaces is implemented using the 0.18��m CMOS process. The self-reference generation technique is proposed to recover data without an equalizer and a reference voltage generator which need large chip areas. The single-ended receiver generates the reference voltage for each bit using the previous bit. The circuit occupies 140�e120�gm2 and dissipates 40mW of power with a supply voltage of 1.8V when 3.2Gbps of data is transmitted over the channel with 18.55dB loss at 1.6GHz. The proposed method significantly reduces the chip area occupied by the receiver, making it adequate for DRAM interfaces.