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Study on Capacitor-less memory cell inserted hole confinement barrier for enhancing memory characteristics

Title
Study on Capacitor-less memory cell inserted hole confinement barrier for enhancing memory characteristics
Other Titles
정공 구속 장벽이 삽입된 무캐패시터 메모리 셀의 메모리 특성 향상에 대한 연구
Author
김성제
Alternative Author(s)
김성제
Advisor(s)
Jea-Gun Park
Issue Date
2011-02
Publisher
한양대학교
Degree
Doctor
Abstract
Dynamic random-access memory (DRAM) play an increasingly important part in determining the performance of electronic products. The memory industry has achieved miracles cramming more memory bits onto ever-smaller silicon die-and selling it for cents. As the feature size scales down to sub-50 nm channel length regime, DRAM is confronted with an important challenge in shrinking the memory cell area. Capacitor-less memory has been proposed as an alternative structure. The conventional storage capacitor has been replaced by the body storage of a silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET). Although Capacitor-less memory has many attractive advantages, the most important problem with its use is short retention time. This motivates the development of innovative Capacitor-less memory cells with enhanced retention time. In this dissertation, various methods for enhancing memory characteristics were studied. First, the dependence of performance on thickness was investigated in Capacitor-less memory on silicon with thicknesses ranging between 15.5 nm and 72.3 nm. It was confirmed that the memory margin depends on the impact ionization rate associated with the increased conduction current density, and that the lateral electric field decreases as the silicon thickness increases. In particular, it was observed that the maximum memory margin is 61 µ
A for a silicon thickness of 45 nm, affording the maximal impact ionization rate. This implies that the optimal silicon thickness is 45 nm for Capacitor-less memory cells operating in fully depleted (FD) SOI n-MOSFETs. Second, the effect of channel doping concentration on the memory margin of Capacitor-less memory cells fabricated on FD SOI n-MOSFETs was investigated. It was observed that the memory margin varies significantly with channel doping concentration, increasing with doping concentrations up to 1.4e17 cm^-3 and then decreasing with higher doping concentrations. In particular, at a concentration of 1.4e17 cm^-3, the memory margin was 1.8 times greater than that at 1.5e15 cm^-3. This gives rise to speculation that the memory margin of Capacitor-less memory cells fabricated on FD SOI n-MOSFETs can be increased by enlarging the lateral electric field and can be decreased by reducing the current density. These results, in turn, suggest that higher memory margins in Capacitor-less memory cells can be obtained by optimizing the channel doping concentration in FD SOI n-MOSFETs. Third, the effects of inserting a strained SiGe layer between the unstrained Si and buried oxide layers and of varying the Ge concentration in this strained SiGe layer on the memory margin of Capacitor-less memory cells were investigated. It was observed that the memory margin of unstrained Si on strained SiGe-on-insulator (SGOI) Capacitor-less memory cells increases with the Ge concentration of the strained SiGe layer
a memory margin 3.2 times larger than that of the SOI cell was obtained at a Ge concentration of 19 at%. This enhancement was due to an exponential increase in potential barrier lowering with increasing Ge concentration, which resulted from higher hole confinement in spite of the reduction in saturated drain current. Finally, the effects of the SiGe layer and mobility enhancement on the memory margin of Capacitor-less memory cells were investigated. The memory margin of a strained Si SGOI Capacitor-less memory cell was 138.6 µ
A, or 3.3 times greater, at a Ge concentration of 32 at%. Two key phenomena contributing to the enhancement of memory margin were studied. One is the effect of hole confinement, which is well achieved by the insertion of the SiGe layer. The other is mobility enhancement due to the strain in the channel. These two effects enhance the memory margin by factors of 1.85 and 1.74, respectively, compared to that of the SOI cell at a 32 at% Ge concentration. The improved memory margins obtained for these strained Si SGOI Capacitor-less memory cells are viable in the era of sub-30 nm-scale memory, and thus the strained Si SGOI Capacitor-less memory cell is an innovative structure with extremely long retention time.
URI
https://repository.hanyang.ac.kr/handle/20.500.11754/139628http://hanyang.dcollection.net/common/orgView/200000415936
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Ph.D.)
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