LCD 오버드라이브 시스템의 메모리 최소화를 위한 효율적인 임베디드 코덱

Abstract

Overdrive is an image processing technology used in T-CON circuit of LCD system. This technology can reduce the response time of liquid crystal and the motion blur in LCD by enlarging the desired change in pixel value between the previous and current frames. To get the previous frame, a frame memory is needed in LCD overdrive system. The using of the frame memory induces some issues such as the cost of frame memory, the operating frequency, the operating current, and pin numbers between LSI and memory. To solve these issues, five embedded compression algorithms are proposed to compress the image data to 1/6 or lower for different applications. The first proposed embedded compression algorithm is the improved motion adaptive codec (IMAC), which contains two approaches to improve motion adaptive codec overdrive (MAC-OD). The first approach is an advanced hybrid image codec (AHIC) for the efficient reduction of the image data stored in frame memory. The second one is an advanced motion adaptive selector to reduce overdrive error. The proposed AHIC converts an RGB image into the YCbCr color space, and compresses the luminance data and the down-sampled chrominance data by using different methods. The second proposed embedded compression algorithm is an adaptive multi-level BTC (AM-BTC) to solve the problem of flicker, which is caused by the inherent limitation of BTC. BTC is commonly used to minimize frame memory in LCD overdrive due to its efficient coding and low implementation cost. However, it causes severe perceptual artifacts and degrades overdrive performance. Therefore, the proposed AM-BTC firstly overcomes the limitation by adaptively selecting 2-level or 4-level BTC according to the edge property of the coding block. Then, to reduce the bit rate of AM-BTC, the 2-level and 4-level BTCs are improved by using only luminance bit-map to represent three color bit-maps. To achieve a low-cost target for frame memory minimization in a low-end LCD overdrive system, a novel cost effective codec (CEC) based on conventional method of block truncation coding (BTC) is also proposed. The proposed algorithm obtains the low-cost target by using fewer line-buffer memories and FPGA resources, and also acquires reasonably robust coding performance by the further compression of bit-maps and representative values which are resulted by BTC encoding. The fourth proposed embedded compression algorithm, a high compression ratio codec (HRC), is presented to compress the image data stored in the on-chip frame memory so that only 1 Mb of on-chip memory is required in the LCD overdrives of mobile devices. The proposed algorithm further compresses the color bit-maps and representative values (RVs) resulting from the BTC. The color bit-maps are represented by a luminance bit-map, which is further reduced and reconstructed using median filter interpolation in the decoder, while the RVs are compressed using AQC. Interpolation and AQC can provide three-level compression, which leads to 16 kinds of combinations. Using a rate-distortion analysis, three optimal schemes are selected to compress the image data for VGA, WVGA, and SD LCD TV applications. Lastly, a lapped transform based codec (LTC) is proposed for frame memory minimization in super-quality LCD overdrive. In the latest literature, a directional prediction based codec (DPC) employs eight directional predictions, which takes up much percentage of hardware cost of the codec, and doesn’t consider the de-correlation of the inter-blocks. Therefore, LTC uses lapped transform to decompose the correlation of inter-blocks in YUV color space, first. Then, a Hadamard transform is used for energy compaction. The reordered coefficients are pre-quantized, and encoded by a proposed adaptive bit-plane coding (ABPC) for simple hardware implementation. The proposed embedded compression algorithms for frame memory minimization in LCD overdrive outperform other competitive researches in subjective and objective performances. The proposed embedded compression algorithms are simulated with C language and implemented in Verilog HDL. Also FPGA platform is used for verification of LCD overdrive system.