1.2V, 130nm CMOS 공정을 이용한 2차 델타시그마 ADC 설계

Abstract

Recently, because of digital convergence of portable multimedia devices, ADCs(analog-to-digital converters) are demanded in multimedia devices such as smartphones, mobile phone, Navigation, and Tablet PC for processing the audio and analog signal more and more. In particular, these devices are operated by a battery and then the portable electronic devices have limited driving time due to limited battery capacity. Therefore, low-voltage and low-power conditions for implementing the ADC circuit became more important. Particularly, for processing the audio and analog signals in the audible signal bandwidth, high resolution above 16 bit might be needed. These delta-sigma ADC has less element matching requirement than Nyquist-rate converters. Therefore, for application requiring high speed, high resolution, and low-power consumption, the delta-sigma modulator is suitable. The main characteristics of the DSM (delta-sigma modulator) are oversampling and noise shaping. In general, the digital circuits take charge of the most signal processing. Therefore, the delta-sigma modulator having low-resolution internal ADC, DAC in feedback loop, and integrators for loop filter can be implemented without the strict matching requirement, so the power consumption of the modulator can be reduced. The digital circuits can be implemented in the standard CMOS process. In this paper, for application of low-voltage, low power audio devices, single bit 2nd order delta-sigma ADC was designed and the structure of the modulator was CIFB (Cascade-of-integrator with feedback form). Especially, to minimize the output swing of OTA and quiescent current of the modulator, we designed 2stage OTA with class-AB output. Because of using class-AB OTA for integrator, the power consumption of the modulator can be reduced. In addition, for high speed driving and low power consumption, we designed latch type comparator for 1-bit quantizer. These delta-sigma modulator can be used for application of a low-power portable devices and high resolution medical equipments such as hearing aids. The core area of the implemented chip was 660㎛ x 770㎛. The modulator was implemented in a 1.2V, 130nm CMOS process. The measured SNR and Dynamic range were 71dB and 73dB. And the power consumption of the modulator was about 100uW.