Low-Power Low-Voltage Delta–Sigma ADCs

Abstract

This dissertation presents low-voltage low-power delta-sigma modulators for audio codecs, high-performance sensors, and biomedical devices. The low-voltage delta–sigma modulator is implemented by using a standard 0.13-μm complementary metal–oxide–semiconductor(CMOS) technology. This research analyzes a subthreshold-leakage current problem in switched-capacitor circuits and proposes subthreshold-leakage suppression switches to solve the problem. The modulator achieves a dynamic range of 83 dB, a peak signal-to-noise ratio(SNR) of 82 dB, and a peak signal-to-noise-plus-distortion ratio(SNDR) of 81 dB in a signal bandwidth of 20 kHz. The power consumption is 34 μW for the modulator. The ultra low-power delta-sigma modulator is implemented by using a standard 0.18-μm CMOS technology. The designed modulator has a dynamic range of49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The high resolution delta-sigma modulator is implemented by using a standard 0.25-μm CMOS technology. Measurement results demonstrate a 89-dB dynamic range in a 20-kHz bandwidth with only 457 μW of power consumption. The figure-of-merit (FOM) comparison of these modulators proves that the presented modulator has highly optimized performance. In addition, It describes the synthesis of a digital decimation filter and testing with an actual chip.