A Study for Improvement of Three-dimensional NAND Flash Memory Program/Erase Speed with Vertical Channel Line

Abstract

Three-dimensional memories have been focused for the future ultra-high density memory technologies to keep a trend of increasing bit density and reducing bit cost since planar type memories have been noticed encountering several device scaling limits. Recently several candidates of the technologies for the future three-dimensional NAND flash cell were proposed, such as Bit Cost Scalable (BiCS) Terabit Cell Array Transistor (TCAT), and Vertical Stacked Array Transistor (VSAT) to achieve aggressive scaling of the device dimension and high memory density [1-3]. Among them, BiCS and TCAT technologies have been focused as the promising candidates for tera-bit NAND flash memory, which can be replaced of the conventional NAND flash memory with floating poly-silicon. Otherwise, an operation speed by an erasing using Gate Induced Drain Leakage (GIDL) for BiCS structure, and complicated process for TCAT have been concerned. For BiCS type, since pillars of NAND string are not connected directly to p-well, erase operation is performed by raising the potential of pillars of NAND string with hole injection which are generated by GIDL near the lower select gate. It typically causes the delay of an erasing speed. In this work, we propose a novel BiCS flash memory with bulk erase operation for better cell characteristics.