A Study of Nonvolatile Memory Using Alloy Nanodot Layer with Extremely High Density

Abstract

The rapid growth of the market for portable electronic appliances requires flash memory devices with high performance such as very large storage density, low power consumption and fast operation. Although Flash memories have been designed as a solution to the scaling problem of conventional EEPROM devices, aggressive scaling of the transistor dimensions and the dramatic increase in the memory array size demand a lower voltage memory cell design for the future. In the case of the tunneling oxide, it must be thin enough to allow a fast write/erase speed at reasonable voltage levels with negligible degradation after 105 programming cycles and thick enough to avoid charge loss during read or normal operations. Thus, all scaling issues pertinent to flash memories are ultimately related to the reliability of the tunneling oxide. Theoretically, in order to ensure ten-year data retention time, the tunneling oxide could be scaled until electron flow through the full oxide thickness becomes significant. However, stress-induced leakage current (SILC) imposes a more stringent limitation on the tunneling oxide can discharge the conduction polysilicon memories was set as thin as about 10 nm from the beginning, and has scarcely been thinned over five successive generations to limit its thickness to 7~8 nm at the present states of nonvolatile memory technology. As a result, the dimension of the FG transistor have been scaled much more slowly than those of the logic transistor, and therefore, the Flash memory performance in terms of access time, write/erase speeds, and operation voltages has not been substantially improves with device scaling. In order to overcome the technological constraints imposed as the device size approach dimensions below the 100 nm range, new memory concepts are needed for ultrahigh density, low-voltage, low-power, and fast write/erase data storage. One of the most promising candidate is nanocrystal memory which has the two-dimensionally distributed FePt nanocrystals inside the gate dielectric of the conventional flash memory. This single-transistor memory device has been introduced as an altermative structure to conventional DRAM for high-storage density and low-power operation, as well as to nonvolatile memories such as Flash EEPROMs for faster write/erase speed, lower write/erase bias, and better endurance. This study report indicated that new non-volatile memory with extremely high density FePt-NDs memory was proposed and fundamental characteristics of the FePt-NDs memory were evaluated. FePt-NDs film is used as a charge retention layer in the FePt-NDs memory. The FePt-NDs film consists of the thin oxide film that dispersively includes high density metal dots with Nano-scale. The FePt-NDs film is formed by using sputtering technique with a special sputtering target. The size and the density of the FePt-NDs in the film are typically 2 nm and around ~1.2x1013/cm2, respectively, which were superior to that of ~ Si or Ge or W and Co quantum dot memory. Non-volatile memory operation at a relatively below ~10 V voltage and 103 endurance characteristic were confirmed in the FePt-NDs memory fabricated according to the conventional MOS process. From these experimental results, we expect that this FePt-NDs device using the FN-tunneling method can be a candidate for the future nonvolatile memory.