직렬 링크를 위한 6.4-Gbit/s 클럭/데이터 복원기 및 직렬화기 설계

Abstract

In order to process 3-D graphics, 3-D vision, and high-definition (HD) video, a dramatic increase in data processing power is required. An increase in processing power requires an increase in the bandwidth of the I/O links, resulting in the adaption of a serial link with point-to-point topology for high-speed I/O links. The desired data rate of the future serial link can be achieved by increasing the timing margins and operating speeds of the interface circuitry, but this comes at the expense of large power dissipation. The timing margin of the receiver using the binary clock/data recovery circuit (CDR) can be reduced by large deterministic jitters in the received data signal and phase error on the sampling clocks. Additional design complexities for increasing the timing margin increase the power dissipation of the receiver. On the transmitter side, a serializer is used to increase the data rate of the serial link. Serializers have significant power dissipation in order to convert the low-speed parallel data into high-speed serial data. As the data rate of the serial link increases with the bandwidth requirements of I/O links, the power efficiency of the serial link becomes a critical design factor. In this dissertation, a CDR and serializer are proposed that can increase the power efficiency of the high-speed serial link. The proposed CDR, which uses a power-efficient eye-tracking loop, increases the power efficiency of the receiver by removing additional circuits in order to increase the integrities of the data and clock. The proposed serializer achieves high power efficiency by using a multiphase structure for high-speed operation and by reducing static power dissipation in the multiphase structure. There are two tracking loops in the proposed CDR: the data-tracking loop (DTL) and the eye-tracking loop (ETL). The two loops control the phases of the sampling clocks with digitally controlled phase interpolators for ease of phase control. The DTL compensates the timing skews between the received data and the sampling clock and tracks the jitter of the data. Because the ETL takes over the clocks from the DTL and tracks the deterministic jitter of the received data signal with low power dissipation, the power efficiency of the receiver can be increased by 3.1%. The ETL can have high jitter tracking bandwidth by removing feedback from the ETL to the DTL. The prototype of the CDR was verified using a 0.18-μm CMOS process. The total power dissipation of the CDR including the phase-locked loop (PLL) is 73.9 mW at 6.4-Gbit/s operation with 1.8-V supply voltage and the power efficiency of the CDR is 11.5 mW/Gbit/s. The proposed CDR achieves low power dissipation by reducing the operating speed of the logic blocks in the CDR to 1/8 of the data rate and by using low-power ETL phase interpolator controller. This results in the power efficiency enhancement of 47.6% compared to the previous eye-tracking CDR. The measured RMS and peak-to-peak jitter of the PLL at the op-eration frequency of 0.8 GHz are 3.9 ps and 34.9 ps, respectively. The RMS and peak-to-peak jitter of the recovered clock are 12.1 and 86.4 ps, respectively. The jitter tolerance of the CDR is 0.5 UI at 10 MHz sinusoidal jitter. In the proposed serializer, a multiphase structure with a differential current-steering output driver is used to achieve the bit-time of the one fanout-of-four (1• FO4) delay. The current-steering output driver reduces the requiring output swing and increases the bandwidth of the serializer. The proposed serializer accomplishes not only high-speed operation, but also low-power dissipation by using a pseudo-nMOS configuration with one-stacked switches and by reducing the short-circuit current of the gate driver in the serializer. The proposed serializer achieves 32.7% reduction in power dissipation compared with the previous high-speed serializer without limiting the operating speed. The prototype of the serializer was verified using a 0.18-μm CMOS process. The measured eye diagram of the transmitter output with a 27 – 1 PRBS pattern at 10-Git/s shows that the eye opening is 75 mV × 58%. The power efficiency of the transmitter is 5.69 mW/Gbit/s at the data rate of 10-Gbit/s.