고해상도 상보형금속산화막반도체 영상 센서용 저전력 소면적 아날로그 디지털 변환기

Abstract

과거 필름을 사용하는 아날로그 영상 획득 장치가 전하결합소자(CCD) 또는 상보형금속산화막반도체(CMOS) 영상 센서 등의 디지털 장치로 대체됨에 따라 영상 센서는 소형화되고 실시간 영상 처리가 가능해져 휴대폰을 비롯한 이동식 장치에서부터 산업용 로봇 및 의료 장비와 같은 장치에 이르기까지 널리 사용되고 있다. 특히 CMOS 영상 센서는 회로의 집적화, 저전력 및 고해상도의 구현이 가능하여 많은 응용 분야에서 사용되고 있다. 공정 및 회로 기술의 발전으로 현재 CMOS 영상 센서의 화소의 크기는 응용분야에 따라 작게는 1 μm에 근접하고 있으며 크게는 200 μm에 이르고 화소의 수는 수백만개 이상으로 증가하게 되었다. 또한, CMOS 영상 센서는 동영상 정보를 얻기 위해 60 frames/s 이상의 설계 규격을 갖는다. 그 결과 CMOS 영상 센서 내에서 디지털 데이터로 변환해야 할 픽셀의 수가 초당 수억개에 이른다. 따라서, CMOS 영상 센서 내에 고속의 아날로그 디지털 변환기(ADC)가 사용되며 이에 전력 소모가 증가하게 된다. 본 논문에서는 고속 고해상도 CMOS 영상 센서에서 전력 소모와 면적을 감소시키기 위한 ADC 설계 기술을 제안한다. 또한 제안된 ADC 설계 기술을 이용해 CMOS 영상 센서를 제작하여 실험을 통해 그 성능을 검증한다. 본 논문에서는 고속 CMOS 영상 센서를 위한 저전력 소면적 컬럼-병렬(column-parallel) 연속 근사(successive approximation, SA) ADC를 제안한다. 일반적인 SA-ADC는 큰 면적을 차지하는 커패시터 디지털 아날로그 변환기(DAC)를 사용하기 때문에 컬럼-병렬 구조에서 구현하기가 쉽지 않다. 제안한 SA-ADC는 커패시터 DAC 대신에 이진 가중치(binary-weighted) 기준 전압을 입력 받아 적분기를 사용하여 기준전압을 생성하는 회로를 사용하여 커패시터 DAC의 면적을 10-비트 기준으로 2.8%의 크기로 감소시켰다. SA-ADC내 사용된 적분기는 CMOS 영상 센서에 필요한 상관된 이중 샘플링(correlated-double sampling, CDS) 기능도 포함하여 별도의 CDS 회로가 필요하지 않다. 적분기 사용에 따른 전력 소모를 감소시키기 위하여 CDS 기간 동안 전류 사용을 제한하는 스위치드 전력(switched-power) 기술을 적용하였다. CMOS 영상 센서의 프레임 속도가 가변되는 조건에서도 ADC의 분해(conversion) 시간을 일정하게 하고 스위치드 전력 기술을 적용하여 15와 150 frames/s 에서 각각 85와 58%의 소비전력 감소 효과를 얻었다. 0.13-μm CMOS 공정을 이용하여 제작된 1.92 메가 픽셀 CMOS 영상 센서는 10-비트의 계조를 가지며 150 frames/s에서 220 mW의 소비전력 특성을 보인다. 회로에 사용되는 면적과 소비전력을 추가로 줄이기 위하여 디지털 영역에서의 컬럼 고정 패턴 잡음(column fixed pattern noise, CFPN) 제거 기술을 사용하였다. 이를 적용하여 CFPN을 6.55에서 0.40 LSB로 감소시켰다. 또한, 고해상도 CMOS 영상센서에서 사용되는 비닝 기술을 구현하기 위한 ADC를 제안하였다. CMOS 영상 센서의 공간 해상도를 낮추고 초당 프레임 수를 증가시키거나 신호대잡음비(SNR)을 향상시키기 위하여 사용하는 비닝 기술은 일반적으로 서브 샘플링이나 전하 증폭기(charge amplifier)를 사용하여 구현된다. 이는 각각 영상의 정확도가 떨어지거나 추가 회로 사용에 의한 소비전력 및 면적 증가의 단점을 가지고 있다. 제안한 ADC는 상위 비트를 분해하고 동시에 비닝 기능을 수행하는 델타-시그마 변조기와 하위 비트를 분해하기 위한 SA-ADC로 구성된 확장 카운트(extended-counting, EC) ADC 이다. 제안된 EC-ADC는 20480개의 디지털 코드를 출력하여 14.3-비트의 유효 분해능을 가진다. 또한, CFPN을 제거하기 위하여 디지털 CDS 기술을 적용하였다. 기존의 CMOS 영상센서에서 디지털 CDS 기능을 적용하기 위해 ADC의 유효 범위의 25%를 사용하여 ADC에서 제공하는 분해범위 전체를 사용할 수 없어 유효 동작 범위(dynamic range)가 제한되었다. 제안된 ADC는 25%의 확장된 범위를 분해할 수 있기 때문에 14-비트의 동작 범위를 사용할 수 있다. 0.35-μm CMOS 공정으로 제작된 14.3-비트 ADC의 DNL(differential non-linearity) 및 INL(integral non-linearity)은 +0.97/-0.79와 +2.79/-1.70 LSB 이고 소비 전력은 150 kS/s에 300 μW 이다. 제작된 EC-ADC를 이용하여 X-선 영상 센서를 구현하여 성공적으로 데모하였다. 제작된 영상 센서는 0.011 mR의 X-ray 선량을 사용할 때 546 μVrms 의 무작위잡음(random noise) 특성을 보이고 67 dB의 유효 동작 범위를 갖는다. 제작된 ADC는 100 μm의 폭을 가지고 있지만 향후 휴대형 영상 센서에도 사용할 수 있도록 SA-ADC의 면적과 소비전력을 줄이기 위한 이단계(two-step) SA-ADC를 추가로 제안하였다. 이단계 SA-ADC는 커패시터 DAC의 면적을 14-비트 ADC 기준으로 이진 가중치 커패시터 DAC 대비 0.15% 그리고 스위칭 에너지는 0.13%로 감소시켰다.|As analog image capturing devices using a film have been replaced by digital devices such as charge-coupled devices(CCDs) and complementary metal-oxide semiconductor(CMOS) image sensors, imagers was miniaturized and capable of performing the real-time image processing. Nowadays, digital imagers are widely used in many applications such as mobile devices, industrial robots, and medical electronics. Especially, CMOS image sensors are increasingly adopted because they have advantages of low-power consumption, high-resolution pixel and circuit integration capabilities. As the CMOS fabrication and circuit design technologies are developed, the pixel size of CMOS image sensors is various from 1 to 200 μm with respect to applications and the number of pixels is higher than 10-megapixels. Also, CMOS image sensors have a frame rate higher than 60 frames/s to acquire moving images. As a result, the number of pixels being converted to the digital code reaches to hundreds of million. Therefore, the very high-speed analog-to-digital converter (ADC) is used in CMOS image sensors, and thereby, the power consumption increases. This dissertation proposes the design techniques of low-power and area-efficient ADC for high-speed and high-resolution CMOS image sensors. The CMOS image sensors using the proposed ADCs were fabricated and its performances are evaluated by experimental demonstration. First, this dissertation proposes low-power and area-efficient column-parallel successive approximation (SA) ADC for high-speed CMOS image sensors. The implementation of the CMOS image sensor with column-parallel SA-ADCs is difficult because conventional SA-ADCs use the capacitor digital-to-analog converter (DAC) occupying large silicon area. The proposed SA-ADC in each column integrates the binary weighted references instead of using a binary-weighted capacitor array to reduce the area, and its area is reduced to 2.8% in the capacitor array for 10-bit conversion. The SA-ADC includes the correlated-double sampling (CDS) function to eliminate the offset error of the pixel circuit. It does not need an additional CDS circuit consuming high power consumption. In order to reduce power consumption of the integrator in the proposed SA-ADC, this dissertation uses the switched-power technique and the constant A/D conversion time. When applying aforementioned low-power techniques, the power consumption of the SA-ADC is reduced to 85 and 58% at the frame frequencies of 15 and 150 frames/s, respectively. The 1.92-megapixel image sensor fabricated using 0.13-μm CMOS process has the 10-bit grayscale and shows 220 mW at 150 frames/s. The column fixed-pattern noise (CFPN) calibration in the digital domain is used to further reduce the power consumption. The CFPN is reduced from 6.55 to 0.40 LSB using the calibration. This dissertation also proposes an ADC with the analog binning function used in high-resolution CMOS image sensors. The binning function, which increases the frame rate or improves signal-to-noise ratio (SNR) by reducing the spatial resolution, is typically implemented using the sub-sampling technique or a charge amplifier circuit. The former loses the image information and the latter dissipates high power and occupies large silicon area. The proposed ADC has an extended-counting (EC) ADC composed of a ΔΣ modulator resolving upper bits and a SA-ADC resolving lower bits. Especially, the ΔΣ modulator also performs the analog binning function. The EC-ADC has a 14.3-bit resolution which means digital output codes of 20480. This work uses the digital CDS technique to reduce CFPN from the offset error of the ADC and pixel. The dynamic range of the ADCs using the digital CDS is reduced because the ADCs use the input range of about 125% to cover the offset error of the ADC and pixel. The EC-ADC with the extended input range of 125% has true 14-bit dynamic range. The proposed 14.3-bit EC-ADC was fabricated using 0.35-μm CMOS process and the measured differential and integral non-linearities of the 14.3-bit ADC are +0.97/-0.79 and +2.79/-1.70 LSB, respectively. The power consumption of the ADC is 300 μW at 150 kS/s. The CMOS X-ray imager using the proposed column-parallel EC-ADCs has a dynamic range of 68.3 dB and a random noise of 461 μVrms at 5 μR. The designed EC-ADC has a column pitch of 100 μm. In order to apply the EC-ADC to mobile applications with small pixel pitch, this dissertation additionally introduces a two-step SA-ADC. Compared with a 14-bit SA-ADC using the binary-weighted capacitor DAC, an area and switching energy of the proposed two-step SA-ADC is reduced to 0.15% and 0.13%, respectively.; As analog image capturing devices using a film have been replaced by digital devices such as charge-coupled devices(CCDs) and complementary metal-oxide semiconductor(CMOS) image sensors, imagers was miniaturized and capable of performing the real-time image processing. Nowadays, digital imagers are widely used in many applications such as mobile devices, industrial robots, and medical electronics. Especially, CMOS image sensors are increasingly adopted because they have advantages of low-power consumption, high-resolution pixel and circuit integration capabilities. As the CMOS fabrication and circuit design technologies are developed, the pixel size of CMOS image sensors is various from 1 to 200 μm with respect to applications and the number of pixels is higher than 10-megapixels. Also, CMOS image sensors have a frame rate higher than 60 frames/s to acquire moving images. As a result, the number of pixels being converted to the digital code reaches to hundreds of million. Therefore, the very high-speed analog-to-digital converter (ADC) is used in CMOS image sensors, and thereby, the power consumption increases. This dissertation proposes the design techniques of low-power and area-efficient ADC for high-speed and high-resolution CMOS image sensors. The CMOS image sensors using the proposed ADCs were fabricated and its performances are evaluated by experimental demonstration. First, this dissertation proposes low-power and area-efficient column-parallel successive approximation (SA) ADC for high-speed CMOS image sensors. The implementation of the CMOS image sensor with column-parallel SA-ADCs is difficult because conventional SA-ADCs use the capacitor digital-to-analog converter (DAC) occupying large silicon area. The proposed SA-ADC in each column integrates the binary weighted references instead of using a binary-weighted capacitor array to reduce the area, and its area is reduced to 2.8% in the capacitor array for 10-bit conversion. The SA-ADC includes the correlated-double sampling (CDS) function to eliminate the offset error of the pixel circuit. It does not need an additional CDS circuit consuming high power consumption. In order to reduce power consumption of the integrator in the proposed SA-ADC, this dissertation uses the switched-power technique and the constant A/D conversion time. When applying aforementioned low-power techniques, the power consumption of the SA-ADC is reduced to 85 and 58% at the frame frequencies of 15 and 150 frames/s, respectively. The 1.92-megapixel image sensor fabricated using 0.13-μm CMOS process has the 10-bit grayscale and shows 220 mW at 150 frames/s. The column fixed-pattern noise (CFPN) calibration in the digital domain is used to further reduce the power consumption. The CFPN is reduced from 6.55 to 0.40 LSB using the calibration. This dissertation also proposes an ADC with the analog binning function used in high-resolution CMOS image sensors. The binning function, which increases the frame rate or improves signal-to-noise ratio (SNR) by reducing the spatial resolution, is typically implemented using the sub-sampling technique or a charge amplifier circuit. The former loses the image information and the latter dissipates high power and occupies large silicon area. The proposed ADC has an extended-counting (EC) ADC composed of a ΔΣ modulator resolving upper bits and a SA-ADC resolving lower bits. Especially, the ΔΣ modulator also performs the analog binning function. The EC-ADC has a 14.3-bit resolution which means digital output codes of 20480. This work uses the digital CDS technique to reduce CFPN from the offset error of the ADC and pixel. The dynamic range of the ADCs using the digital CDS is reduced because the ADCs use the input range of about 125% to cover the offset error of the ADC and pixel. The EC-ADC with the extended input range of 125% has true 14-bit dynamic range. The proposed 14.3-bit EC-ADC was fabricated using 0.35-μm CMOS process and the measured differential and integral non-linearities of the 14.3-bit ADC are +0.97/-0.79 and +2.79/-1.70 LSB, respectively. The power consumption of the ADC is 300 μW at 150 kS/s. The CMOS X-ray imager using the proposed column-parallel EC-ADCs has a dynamic range of 68.3 dB and a random noise of 461 μVrms at 5 μR. The designed EC-ADC has a column pitch of 100 μm. In order to apply the EC-ADC to mobile applications with small pixel pitch, this dissertation additionally introduces a two-step SA-ADC. Compared with a 14-bit SA-ADC using the binary-weighted capacitor DAC, an area and switching energy of the proposed two-step SA-ADC is reduced to 0.15% and 0.13%, respectively.