3D ICs를 위한 floorplan 단계에서의 라우팅 혼잡도 측정과 최적화

Abstract

The recent popularity of three dimensional integrated circuits (3D ICs) technology stems from its higher integrated degree and enhanced performance. However, higher integrated and smaller chip area also bring more serious routability problem, which will degrade circuit performance or even lead to routing failure. Thus, for 3D ICs, an accuracy and effective congestion estimation method to predict routability in the early designing stages such as floorplan stage is proposed. The proposed method is based on probabilistic analysis and it takes the location of through silicon vias (TSVs) into consideration. Additionally, an effective congestion aware floorplan used the proposed estimation model is demonstrated. Firstly, the initial floorplanning is generated based on the simulated annealing algorithm which only focuses on the chip area and total wirelength. With the proposed estimation method, the congestion degree of each grid could be calculated. Then a proposed optimization algorithm is described in this thesis, which moves or swaps blocks away from the over-congested area to achieve the optimization of routing congestion. Experiments show the application of congestion aware floorplan can reduce the maximum routing congestion about 46.4% at most.