3D ICs를 위한 floorplan 단계에서의 라우팅 혼잡도 측정과 최적화
- Title
- 3D ICs를 위한 floorplan 단계에서의 라우팅 혼잡도 측정과 최적화
- Other Titles
- Routing Congestion Estimation and Optimization at Floorplan Stage for 3D ICs
- Author
- 이문예
- Alternative Author(s)
- Wenrui Li
- Advisor(s)
- 정정화
- Issue Date
- 2012-08
- Publisher
- 한양대학교
- Degree
- Master
- Abstract
- The recent popularity of three dimensional integrated circuits (3D ICs) technology stems
from its higher integrated degree and enhanced performance. However, higher integrated and
smaller chip area also bring more serious routability problem, which will degrade circuit
performance or even lead to routing failure. Thus, for 3D ICs, an accuracy and effective
congestion estimation method to predict routability in the early designing stages such as floorplan
stage is proposed. The proposed method is based on probabilistic analysis and it takes the location
of through silicon vias (TSVs) into consideration.
Additionally, an effective congestion aware floorplan used the proposed estimation model is
demonstrated. Firstly, the initial floorplanning is generated based on the simulated annealing
algorithm which only focuses on the chip area and total wirelength. With the proposed estimation
method, the congestion degree of each grid could be calculated. Then a proposed optimization algorithm is described in this thesis, which moves or swaps blocks away from the over-congested
area to achieve the optimization of routing congestion. Experiments show the application of
congestion aware floorplan can reduce the maximum routing congestion about 46.4% at most.
- URI
- https://repository.hanyang.ac.kr/handle/20.500.11754/135941http://hanyang.dcollection.net/common/orgView/200000419837
- Appears in Collections:
- GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Master)
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