A Study on Erase Speed Enhancement of 3D Vertical NAND Flash Memories by using Bulk-Erasable Electrodes
- Title
- A Study on Erase Speed Enhancement of 3D Vertical NAND Flash Memories by using Bulk-Erasable Electrodes
- Author
- 김경록
- Alternative Author(s)
- Kim Kyeong-rok
- Advisor(s)
- 송윤흡
- Issue Date
- 2013-02
- Publisher
- 한양대학교
- Degree
- Doctor
- Abstract
- A bit-cost scalable (BiCS) technology using a bulk erasing method instead of the conventional erase operation using gate-induced drain leakage (GIDL) is proposed to realize better cell characteristics and process feasibility for three-dimensional (3D) NAND flash memory. A novel 3-dimensional (3-D) vertical stacked type NAND flash cell arrays using the bulk erase method is proposed. This cell arrays consist of has an additional electrode layer for a bulk erase operation in the middle of a vertical channel string cell and several rows of NAND string share control gates. We investigated the I-V characteristics of the bulk erasable-BiCS structure using 3-D TCAD simulation tool, rely on the P+ bulk electrode for high speed Program/Erase operation and good read current margin. Here, we confirmed that this novel cell technology provides better cell characteristics and process feasibility for the 3-D vertical stacked NAND flash cell arrays. Morever, junction (P+/P/P+) engineering is achieved to realize a P+ poly-crystalline silicon layer of the P+ flat plate type as a bulk electrode for better design feasibility. As a result, we expect that a bulk erasable-BiCS technology using a P+ flat plate type erase electrode can be a promising candidate tera-bit 3-dimensional vertical stacked NAND flash memory technology in the near future.
- URI
- https://repository.hanyang.ac.kr/handle/20.500.11754/134261http://hanyang.dcollection.net/common/orgView/200000420803
- Appears in Collections:
- GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Ph.D.)
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