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Simulation benchmarking for the whole resist process

Title
Simulation benchmarking for the whole resist process
Author
오혜근
Keywords
Benchmark; Lithography; Photolithography; Process latitude; Simulation; Solid-C
Issue Date
2004-04
Publisher
SPIE
Citation
Proceedings of SPIE - The International Society for Optical Engineering, v. 5378, Page. 58-64
Abstract
A full lithography simulation has become an essential factor for semiconductor manufacturing. We have been researching all kinds of problems for lithography process by creating and using our own simulation tool, which has contributed to extracting parameters related to exposure, post exposure bake, and development. Also, its performance has been proved in comparison with other simulation tools. In this paper, our lithography simulator and some of its features are introduced. For its benchmark, we describe our own simulator's performance and accuracy for whole resist process by the comparison of a commercial tool. The sensitivity of process parameters and process latitude due to its parameters are discussed.
URI
https://repository.hanyang.ac.kr/handle/20.500.11754/132070https://www.spiedigitallibrary.org/conference-proceedings-of-spie/5378/1/Simulation-benchmarking-for-the-whole-resist-process/10.1117/12.536210.short
ISSN
0277-786X
DOI
10.1117/12.536210
Appears in Collections:
COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY[E](과학기술융합대학) > APPLIED PHYSICS(응용물리학과) > Articles
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