Precision Measurement Methods and Physical Analysis of Device Characteristics for High-Performance Analog Semiconductor Fabrication Process

Abstract

지난 수십 년간 반도체 공정 기술은 급속도로 발전을 해왔으며, 반도체 집적회로를 적용한 많은 IT 제품들을 탄생시키는 중요한 역할을 하였다. 최근에는 스마트폰, 자동차, 의료용 기기 등 많은 응용 분야가 반도체 기술과 결합하여, 새로운 IT 융합 기술을 선도해 가고 있다. 반도체 공정 기술을 사용하여 제작되는 회로들은 신호 처리 방법에 따라 크게 아날로그 집적회로와 디지털 집적회로로 분류하며, 각 집적회로의 특성에 따라 필요한 반도체 공정 기술이 다르다. 따라서 반도체 공정 기술은 집적회로의 필요사항에 부합되도록 연구되고 발전되어 왔다. 메모리, 마이크로프로세서, FPGA 등의 디지털 집적회로를 제작하는 공정의 경우에는, 소자의 집적도를 향상시키기 위해서 소자의 크기와 금속 배선의 선폭을 감소시키는 것에 중점을 두어 연구를 진행해 왔다. 그 결과, 많은 연구자들의 노력에 의해서 소자의 크기와 공정 배선의 선폭은 지속적으로 감소되어 왔으며 현재는 십여 nm까지 줄이는 성과를 이루었다. 반면에 아날로그 집적회로를 제작할 수 있는 반도체 공정기술은 소자의 크기를 줄이기 위한 연구와 하나의 칩 상에 여러 소자를 집적할 수 있는 연구가 함께 진행되어 왔다. 그러나 아날로그 집적회로와 아날로그 신호 크기의 다양성 때문에 디지털 집적회로를 위한 반도체 공정 기술에 비하여 아날로그 집적회로를 위한 반도체 공정 기술의 개발 성과가 부족한 현실이다. 따라서 여러 IT 융합 분야에 사용되기 위해서 연구되고 있는 고성능 아날로그 집적회로를 위하여 반도체 공정 기술을 향상시켜야 하는 필요성이 부각되고 있다. 많은 전자제품에 집적되는 아날로그 회로들은 인간이 인지할 수 있는 현실 세계와 디지털 세계사이의 연결을 해주는 통로 역할을 하게 된다. 따라서 디지털 회로에서 중시하는 칩 면적, 가격, 그리고 소비 전력과 같은 항목을 개선시키기 위한 노력과는 다르게, 아날로그 회로에서는 전체적인 아날로그 성능, 전력 효율, 그리고 신뢰성 같은 항목들이 주요한 고려사항이다. 본 논문에서는 아날로그 회로의 성능을 향상시키기 위하여 아날로그 회로에 특화된 소자의 성능을 측정할 수 있는 새로운 측정 방법과 집적되는 소자들의 아날로그 성능 향상을 위한 공정 최적화 방법과 분석 방법 등을 제안하였다. 첫 번째로 아날로그 회로 내에서 많은 면적을 차지하는 캐패시터를 최적화할 수 있는 방법들을 제안하였다. 캐패시터를 최적화하기 위해서는 캐패시터의 특성을 정밀하게 측정할 수 있는 측정 방법이 필요하지만, 캐패시터의 비이상적인 특성들을 측정하는 기존의 방법들은 측정 정확도와 신뢰도가 낮다는 문제점을 가지고 있다. 제안된 측정 방법 중 하나는 스위치드 커패시터 증폭기를 사용하여 캐패시터 배열의 부정합을 정밀하게 측정하는 방법이다. 다른 하나는 캐패시터의 비이상적인 특성인 유전흡수를 측정할 수 방법으로, 스위치의 오프-누설전류가 없도록 제어가 가능하고 외부 잡음의 면역력을 증대시킬 수 있도록 증폭기를 사용한 온-칩 측정 방법이다. 제안한 측정 방법의 성능을 정량적으로 평가하기 위하여 반복적인 측정을 통하여 측정의 정확도와 신뢰도를 검증하였다. 그 결과 커패시터의 부정합 특성을 측정하는 방법은 기존 방법 대비 10배의 측정 정확도와 신뢰도를 갖는다는 것을 확인하였으며, 커패시터의 유전흡수 측정 방법은 99.9% 이상의 측정 정확도와 신뢰도를 갖는 다는 것을 입증하였다. 두 번째로 아날로그 회로 내에 집적되는 저항의 특성을 개선하기 위하여, SiCr (silicon chromium) 박막 저항의 제조공정을 제안하고 최적화 되었다. 공정 최적화를 위하여 여러 공정 조건에 따른 제안한 SiCr 박막저항의 특성을 평가하였으며, 이를 통하여 제안한 SiCr 박막저항이 매우 우수한 특성을 갖는 다는 것을 확인하였다. 측정 결과 온도에 따른 저항 계수는 −3.9 ppm/℃ 이며 저항의 부정합 특성은 0.34 %•μm 이다. 이 결과들은 기존의 발표된 박막저항 중에 가장 뛰어난 온도 특성과 부정합 특성을 나타내며, 이는 제안한 SiCr 박막저항이 아날로그 회로 내에 사용되기에 매우 우수한 소자라는 것을 나타낸다. 마지막으로 아날로그 CMOS 소자의 1/f 잡음 특성이 아날로그 회로의 잡음 성능에 미치는 영향에 대하여 연구하였다. 이를 위하여 여러 공정 조건에 따라 CMOS 소자와 저잡음 증폭기를 설계하고 측정하였다. 측정 결과를 통하여 저잡음 증폭기의 잡음 특성과 CMOS 소자의 1/f 잡음 특성간의 관계를 확인하였으며, 그 결과 아날로그 ICs의 잡음 특성을 향상시킬 수 있는 최적화 된 공정을 평가할 수 있었다. 결론적으로 공정 조건에 따라 CMOS 소자의 1/f 잡음 특성을 제어함으로써 아날로그 ICs의 잡음 특성을 향상시킬 수 있다는 결론을 도출하였다. |Semiconductor process technologies have rapidly evolved during the past several decades and have contributed to develop the state-of-the-art IT products by employing semiconductor integrated circuits (ICs). In recent years, semiconductor technology is converged with diverse application products such as smart phone, automobile, and medical device, thereby leading the new IT convergence technology. Semiconductor ICs are broadly classified into analog IC and digital IC according to the method of the signal processing. Their required processes are differed by the type of fabricated IC. Therefore, semiconductor process technologies have been researched and developed in accordance with the technology trend and the demand of IC designers. In case of digital ICs such as memories, microprocessors, and field-programmable gate array, the size of an integrated device and the width of an interconnection metal have been continuously decreased to improve the density of the process. Consequently, the metallization line of the semiconductor process for digital ICs has been reduced to several tens of nm by efforts of many researchers. In case of analog ICs, the semiconductor process technology has been developed to reduce the device size and to integrate multiple devices on a single chip. However, the progress of the semiconductor process technology for analog ICs is far behind compared to that of the digital ICs because the considerations and application areas of analog ICs are much more diverse. Therefore, it is necessary to develop a better analog process technology for high performance analog ICs. Many analog ICs in electronic products play an important role as a bridge between the real world and the digital world. Design considerations such as chip size, cost, and power consumption are important for digital ICs, whereas overall analog performances (precision accuracy, linearity, sensitivity, dynamic range, and etc.), power efficiency, and robustness are carefully taken into consideration for analog ICs. Accordingly, the analog performance enhancement and accurate characterization of integrated devices should be considered with greatest importance for high performance analog ICs. To that end, this dissertation presents novel measurement methods to specify analog device properties, process optimization methods, and the physical analysis to improve analog performances of integrated devices. Firstly, novel measurement methods are proposed to measure non-ideal properties of the integrated capacitors which occupy a large area in analog ICs. In general, precision measurement methods are indispensable to optimize the properties of integrated capacitor. However, conventional measurement methods have critical problems in the measurement accuracy and reliability for non-ideal properties of integrated capacitor. One of the proposed methods is the mismatch measurement method for integrated capacitor arrays using switched capacitor amplifier. The other is the on-chip measurement method for dielectric absorption (DA), one of the non-ideal properties of integrated capacitor. This method employs switches without off-leakage current and a readout amplifier to minimize the influence of external noise. To quantitatively estimate the performance of the proposed methods, the measurement accuracy and reliability are verified through repetitive measurements. The measurement results show that the accuracy and reliability of the proposed method to measure mismatch of integrated capacitor array are ten times better than those of conventional method. The measurement accuracy and reliability of the proposed method to measure DA of the integrated capacitor is demonstrated over 99.9%. Secondly, in order to improve the characteristics of integrated resistors, the fabrication process of the integrated silicon chromium (SiCr) thin film resistor (TFR) is proposed and optimized for high-performance analog ICs. The characteristics of the proposed SiCr TFR are measured according to several process parameters. The measured temperature coefficient of resistance (TCR) and mismatch slope are −3.9 ppm/℃ and 0.34 %•μm, respectively. These results indicate that the proposed SiCr TFR performs better than conventional TFRs, and appears to be a good candidate for implementing high-precision analog circuits. Finally, the noise performance of analog ICs is verified according to 1/f noise of the CMOS device. CMOS and low noise amplifier (LNA) were fabricated and measured under several process conditions. The noise performance of analog ICs is optimized and the relationship between the noise performance of fabricated LNA and 1/f noise of CMOS is analyzed using the measured results. Consequently, the improved noise performance of analog ICs is demonstrated by optimizing 1/f noise of CMOS process according to the process conditions.; Semiconductor process technologies have rapidly evolved during the past several decades and have contributed to develop the state-of-the-art IT products by employing semiconductor integrated circuits (ICs). In recent years, semiconductor technology is converged with diverse application products such as smart phone, automobile, and medical device, thereby leading the new IT convergence technology. Semiconductor ICs are broadly classified into analog IC and digital IC according to the method of the signal processing. Their required processes are differed by the type of fabricated IC. Therefore, semiconductor process technologies have been researched and developed in accordance with the technology trend and the demand of IC designers. In case of digital ICs such as memories, microprocessors, and field-programmable gate array, the size of an integrated device and the width of an interconnection metal have been continuously decreased to improve the density of the process. Consequently, the metallization line of the semiconductor process for digital ICs has been reduced to several tens of nm by efforts of many researchers. In case of analog ICs, the semiconductor process technology has been developed to reduce the device size and to integrate multiple devices on a single chip. However, the progress of the semiconductor process technology for analog ICs is far behind compared to that of the digital ICs because the considerations and application areas of analog ICs are much more diverse. Therefore, it is necessary to develop a better analog process technology for high performance analog ICs. Many analog ICs in electronic products play an important role as a bridge between the real world and the digital world. Design considerations such as chip size, cost, and power consumption are important for digital ICs, whereas overall analog performances (precision accuracy, linearity, sensitivity, dynamic range, and etc.), power efficiency, and robustness are carefully taken into consideration for analog ICs. Accordingly, the analog performance enhancement and accurate characterization of integrated devices should be considered with greatest importance for high performance analog ICs. To that end, this dissertation presents novel measurement methods to specify analog device properties, process optimization methods, and the physical analysis to improve analog performances of integrated devices. Firstly, novel measurement methods are proposed to measure non-ideal properties of the integrated capacitors which occupy a large area in analog ICs. In general, precision measurement methods are indispensable to optimize the properties of integrated capacitor. However, conventional measurement methods have critical problems in the measurement accuracy and reliability for non-ideal properties of integrated capacitor. One of the proposed methods is the mismatch measurement method for integrated capacitor arrays using switched capacitor amplifier. The other is the on-chip measurement method for dielectric absorption (DA), one of the non-ideal properties of integrated capacitor. This method employs switches without off-leakage current and a readout amplifier to minimize the influence of external noise. To quantitatively estimate the performance of the proposed methods, the measurement accuracy and reliability are verified through repetitive measurements. The measurement results show that the accuracy and reliability of the proposed method to measure mismatch of integrated capacitor array are ten times better than those of conventional method. The measurement accuracy and reliability of the proposed method to measure DA of the integrated capacitor is demonstrated over 99.9%. Secondly, in order to improve the characteristics of integrated resistors, the fabrication process of the integrated silicon chromium (SiCr) thin film resistor (TFR) is proposed and optimized for high-performance analog ICs. The characteristics of the proposed SiCr TFR are measured according to several process parameters. The measured temperature coefficient of resistance (TCR) and mismatch slope are −3.9 ppm/℃ and 0.34 %•μm, respectively. These results indicate that the proposed SiCr TFR performs better than conventional TFRs, and appears to be a good candidate for implementing high-precision analog circuits. Finally, the noise performance of analog ICs is verified according to 1/f noise of the CMOS device. CMOS and low noise amplifier (LNA) were fabricated and measured under several process conditions. The noise performance of analog ICs is optimized and the relationship between the noise performance of fabricated LNA and 1/f noise of CMOS is analyzed using the measured results. Consequently, the improved noise performance of analog ICs is demonstrated by optimizing 1/f noise of CMOS process according to the process conditions.