STT-MRAM을 위한 동작완료 인지 가능한 저전력 쓰기동작 회로

Abstract

STT-MRAM은 차세대 비휘발성 메모리로써 기존 메모리를 대체할 것으로 예상되고 있다. DRAM 수준의 집적도와 SRAM처럼 빠른 속도, Flash의 비휘발성을 모두 갖춘 STT-MRAM은 미래 소자로 각광받기에 충분하다. 그러나 STT-MRAM의 핵심 소자인 MTJ에는 여전히 해결해야 할 문제가 존재하며 이러한 문제요소는 STT-MRAM의 상용화에 제약이 된다. 본 논문에서는 STT-MRAM의 기본적인 쓰기동작과 핵심 소자인 MTJ 셀에 관해 분석함으로써 이러한 단점을 파악하여 상용화에 제약이 되는 이유에 대해 논의한다. 논의를 통해 이를 극복하기 위하여 본 논문에서 제안하는 STT-MRAM을 위한 동작완료 인지 가능한 저전력 쓰기동작 회로와 재구성 가능한 기본 셀에 대한 설명하고자 한다. 기존의 쓰기동작과 읽기동작은 구분되어왔지만 제안하는 쓰기동작 회로는 기존의 쓰기동작 회로와 구조적으로 다르며 읽기동작에서 사용되는 감지회로와 유사한 동작을 응용하였다. 따라서 제안하는 쓰기동작 회로는 쓰기동작 과정에서도 상태 전환을 인지하여 확률적인 상태전환에 능동적으로 대응할 수 있으며 불필요한 전력소모를 줄일 수 있다. 또한 기존의 쓰기동작 회로에서 MTJ 불량 등에 의해 발생할 수 있는 오동작에 대해서도 대응할 수 있는 강인회로로써 동작한다. 재구성 가능한 기본 셀은 공정 미스매치나 반복된 쓰기동작으로 인한 MTJ 히스테리시스의 성능 저하에도 정상 동작이 이루어질 수 있도록 한다. 특히 MTJ 히스테리시스의 기울기 변화로 인한 유효 TMR의 저하에도 대응할 수 있는 보상 회로로써 동작할 수 있다. 본 논문의 제안된 구조는 0.13 um CMOS 공정을 이용하여 설계했고 VDD=1.2V인 조건에서 시뮬레이션을 통해 검증하였다. MTJ 셀은 Verilog-A code를 사용하여 모델링하였고 MTJ 특성은 TMR=100%, RA=5Ω•um2 으로 설정하였다. MTJ 모델에는 확률적인 상태전환을 반영하였으며 상태전환 시간의 분산을 설정할 수 있도록 하였다. 상태전환 시간의 분산을 네 가지 경우로 나누어 Monte Carlo 시뮬레이션을 진행하였으며 가장 큰 분산 값을 갖는, 즉 MTJ의 확률적인 상태전환 시간의 최대시간과 최소시간의 차가 11ns인 경우에 대해 평균 59%의 전력소모를 절약할 수 있었다. 따라서 제안된 동작완료 인지 가능한 저전력 쓰기동작 회로는 상태전환 인지회로를 추가하여 쓰기동작 중에 상태전환이 일어나면 동작을 종료시킬 수 있도록 하여 기존의 구조보다 전력소모가 줄었으며 MTJ 셀의 확률적인 상태전환의 분산값이 클수록 효과적인 구조임을 시뮬레이션을 통해 확인 하였다. |STT-MRAM is one of a next generation non-volatile memory and expected to substitute conventional memories such as DRAM and SRAM. Because of high density of integration which is a feature of DRAM, high speed process which is a feature of SRAM and non-volatility which is a feature of Flash, STT-MRAM is sufficient to be in the limelight. But MTJ which is main device of STT-MRAM still has issues which restrict its commercialization and need to be solved. In this thesis, low power write operation circuit with detection for STT-MRAM is presented to overcome the drawbacks of the MTJ which were announced previously and devise reconfigurable MTJ reference cell. In the conventional STT-MRAM circuit, write circuit and read circuit were classified. But proposed scheme applied sensing circuit which is used only in read circuit and is different from conventional scheme in operation perspective. Proposed scheme can deal with stochastic switching dynamically which is feature of the MTJ and save needless power consumption occurred in conventional write scheme. Reconfigurable MTJ reference cell ensures proper operation and is adaptive for performance degradation especially slope variation. MTJ cell was modeled with Verilog-A containing stochastic feature of MTJ and availability of setting variance of stochastic switching time. MTJ model and the proposed circuit were simulated with 130nm CMOS process and supply voltage was 1.2V. Specification of the MTJ was set up as 100% TMR and 5Ω•um2 of RA. Stochastic switching feature was applied to the MTJ model and Monte Carlo simulation was presented with four case of variance of the switching time. In the case of time variance equals to 11ns, power consumption was saved about 59% compared to conventional STT-MRAM write scheme. As a result, the proposed low power write operation circuit with detection achieved effective power saving performance with simulation of variance of stochastic switching time. It is efficient compared to conventional scheme and much effective on the case of MTJ having large variance of stochastic switching time.; STT-MRAM is one of a next generation non-volatile memory and expected to substitute conventional memories such as DRAM and SRAM. Because of high density of integration which is a feature of DRAM, high speed process which is a feature of SRAM and non-volatility which is a feature of Flash, STT-MRAM is sufficient to be in the limelight. But MTJ which is main device of STT-MRAM still has issues which restrict its commercialization and need to be solved. In this thesis, low power write operation circuit with detection for STT-MRAM is presented to overcome the drawbacks of the MTJ which were announced previously and devise reconfigurable MTJ reference cell. In the conventional STT-MRAM circuit, write circuit and read circuit were classified. But proposed scheme applied sensing circuit which is used only in read circuit and is different from conventional scheme in operation perspective. Proposed scheme can deal with stochastic switching dynamically which is feature of the MTJ and save needless power consumption occurred in conventional write scheme. Reconfigurable MTJ reference cell ensures proper operation and is adaptive for performance degradation especially slope variation. MTJ cell was modeled with Verilog-A containing stochastic feature of MTJ and availability of setting variance of stochastic switching time. MTJ model and the proposed circuit were simulated with 130nm CMOS process and supply voltage was 1.2V. Specification of the MTJ was set up as 100% TMR and 5Ω•um2 of RA. Stochastic switching feature was applied to the MTJ model and Monte Carlo simulation was presented with four case of variance of the switching time. In the case of time variance equals to 11ns, power consumption was saved about 59% compared to conventional STT-MRAM write scheme. As a result, the proposed low power write operation circuit with detection achieved effective power saving performance with simulation of variance of stochastic switching time. It is efficient compared to conventional scheme and much effective on the case of MTJ having large variance of stochastic switching time.