고성능 델타-시그마 모듈레이터설계

Abstract

시스템반도체 시장은 스마트폰과 태블릿PC가 대중화되며 폭발적으로 성장하였다. 최근 차세대 정보통신기술산업에 대한 열망이 매우 높아지면서 사물인터넷이라는 개념이 뜨겁게 주목을 받으며 지속적으로 발전할 것으로 예상된다. 따라서 본 학위 논문에서는 대역폭에 따른 과표본화 델타-시그마 모듈레이터의 설계기법을 연구하였다. 첫 번째 연구에서는 넓은 대역폭을 가지는 신호를 처리하기 위한 델타-시그마 모듈레이터를 소개하였다. 그리고 고속 저전력 설계에 적합한 입력 피드포워드 델타-시그마 모튤레이터를 사용하며 발생되는 문제점을 제시하고 해결하였다. 기존의 입력 피드포워드 구조를 사용한 델타-시그마 모듈레이터는 적분기 출력스윙이 감소하여 증폭기의 요구조건 완화되지만 합산회로가 필요하여 추가적인 전력, 면적, 시간을 소비하게 된다. 이 연구에서는 추가적인 합산회로를 제거한 구조를 사용하여 기존방식이 가졌던 문제점을 개선하기 위한 회로를 제안한다. 제안된 회로는 합산회로를 제거함으로 인해 고속의 동작이 가능하고 전력소모를 약 20 %를 감소시켰다. 두 번째 연구에서는 좁은 대역폭을 가지는 정전용량센서를 위한 증분형 델타-시그마 모듈레이터를 소개한다. 설계한 증분형 델타-시그마 ADC 는 기존의 델타-시그마 ADC의 구조를 그대로 가지고 클럭의 개수마다 변환하도록 리셋신호를 추가한 구조로서 센서로부터 전달되는 저주파 신호를 입력 받아 입력의 변환주기 동안만 동작하여 다채널 변환에 용이하다. 이 연구에서는 센서의 변화를 전압으로 변환하는 회로를 제거하고 직접 변환하는 증분형 델타-시그마 ADC를 설계하였다. 기생커패시턴스에 의한 영향을 완화시키기 위해 1차로 차폐신호를 주변에 배치하고 2차로 20 pF 범위를 가지는 6-비트 오프셋 DAC를 배치하였다. 주변 잡음에 강한 델타-시그마 ADC와 마이크로 컨트롤러를 완전 집적화한 칩의 동작을 확인하였다. 본 논문에서 제안된 회로들은 standard CMOS 공정을 이용하여 제작되었고, HSPICE 시뮬레이션 및 측정을 통해 기능이 검증되었다.|The growing use of smartphones and tablet PCs has brought about explosive growth in the system semiconductor market. Continued growth is expected, based on the expanding interest in the concept termed the internet of things and the sharp heightening of the aspirations for next-generation information communication technology. This dissertation research examined the design techniques for oversampling delta-sigma modulators according to the bandwidth. The first study introduced a delta-sigma modulator for processing signals with wide bandwidth applications. Problems arising in the development of input-feedforward delta-sigma modulators suitable for high speed and low power design were also introduced and solved. The delta-sigma modulators made using existing input-feed-forward structures, although they decrease the requirements for amplifiers by decreasing integrator output swings, have greater consumption of power, area, and time because they require a summing circuit. This research proposed the circuit that would solve the problem in the existing method by using a structure that removes the additional summing circuit. This removal allows the proposed circuit to operate at high speed while consuming approximately 20 % less power. The second study introduces an incremental delta-sigma modulator for capacitive sensors with narrow bandwidths. The designed incremental delta-sigma analog-to-digital converter (ADC) has the same structure as that of existing delta-sigma ADCs except that reset signals were added so that inputs can be converted at intervals of a certain number of clocks. The ADC therefore receives low frequency signals transmitted from the sensor so that it operates only during the input conversion periods, making it advantageous for multi-channel conversion. The proposed structure removes the circuit that converts changes in sensors into voltages and replaces it with an incremental delta-sigma ADC that directly converts the signals. The effects of parasitic capacitance are removed by arranging shielding signals around the incremental delta-sigma ADC and then adding a 6-bit offset digital-to-analog converter (DAC) having a range of 20 pF. The chip with a delta-sigma ADC that is effective against surrounding noises was completely integrated with a micro controller. The circuits proposed in this research were fabricated using the standard complementary metal-oxide-semiconductor (CMOS) process and their functions were verified through HSPICE simulations and measurement.; The growing use of smartphones and tablet PCs has brought about explosive growth in the system semiconductor market. Continued growth is expected, based on the expanding interest in the concept termed the internet of things and the sharp heightening of the aspirations for next-generation information communication technology. This dissertation research examined the design techniques for oversampling delta-sigma modulators according to the bandwidth. The first study introduced a delta-sigma modulator for processing signals with wide bandwidth applications. Problems arising in the development of input-feedforward delta-sigma modulators suitable for high speed and low power design were also introduced and solved. The delta-sigma modulators made using existing input-feed-forward structures, although they decrease the requirements for amplifiers by decreasing integrator output swings, have greater consumption of power, area, and time because they require a summing circuit. This research proposed the circuit that would solve the problem in the existing method by using a structure that removes the additional summing circuit. This removal allows the proposed circuit to operate at high speed while consuming approximately 20 % less power. The second study introduces an incremental delta-sigma modulator for capacitive sensors with narrow bandwidths. The designed incremental delta-sigma analog-to-digital converter (ADC) has the same structure as that of existing delta-sigma ADCs except that reset signals were added so that inputs can be converted at intervals of a certain number of clocks. The ADC therefore receives low frequency signals transmitted from the sensor so that it operates only during the input conversion periods, making it advantageous for multi-channel conversion. The proposed structure removes the circuit that converts changes in sensors into voltages and replaces it with an incremental delta-sigma ADC that directly converts the signals. The effects of parasitic capacitance are removed by arranging shielding signals around the incremental delta-sigma ADC and then adding a 6-bit offset digital-to-analog converter (DAC) having a range of 20 pF. The chip with a delta-sigma ADC that is effective against surrounding noises was completely integrated with a micro controller. The circuits proposed in this research were fabricated using the standard complementary metal-oxide-semiconductor (CMOS) process and their functions were verified through HSPICE simulations and measurement.