A Study on Design of Robust Sense Amplifier to Overcome the Effect of Parameter Variation for STT-MRAM Cell

Abstract

Recently, memory industry faces significant disruption for a great change. Most commonly used memories in present are NAND flash memory, DRAM, and SRAM. NAND Flash memory is non-volatile memory used for storage element of solid-state drive (SSD) and portable universal serial bus (USB) memory device by using charging a floating gate. On the other hand, DRAM, which consists of one transistor and one capacitor as a cell, is volatile memory that requires power to maintain stored information. DRAM has a small cell size and a high operation speed, but has large power consumption due to refresh. Since a minimum capacitance should be required to secure the valid data, the fabrication process has been getting complex and difficult. On the contrary, NAND flash memory has an advantage of storage density because of their simple cell structure, and can be possible to make not also three-dimensional stacked memory but also multilevel cell. However, an operation speed is very slow more than DRAM due to charge trapping or de-trapping. SRAM has fast operation speed, but has large cell area size by using 4-6 transistors for one cell and volatile characteristic. Therefore, the memory industries suffer from a development of a “universal memory” having the advantages of each memory. A spin-transfer-torque magneto-resistive random access memory (STT-MRAM) is an excellent candidate for a “universal memory”. The universal memory should be able to encompass an outstanding performance, which has non-volatility, and a fast operation speed, low power consumption, and an infinite number of write cycles. Therefore, STTMRAM can offer the enhanced performance for digital equipment on Internet of Things (IOT), which requires very fast operation speed and maintains the data in spite of the equipment power off such as an instant ON-state and quick software change. A STTMRAM consists of a thin tunnel oxide barrier between two ferromagnetic layers, which is called a magnetic tunnel junction (MTJ). The conductance of the MTJ depends on the magnetization vector of ferromagnetic layers. The magnetization vector in one of ferromagnetic layers (called pinned layer) is fixed and in the other ferromagnetic layer (called free layer) is variable. The magnetization vector between free and pinned layers has a parallel or antiparallel state. The MTJ resistance of the anti-parallel state (high state) is larger than the resistance of the parallel state (low state). The difference in conductance according to magnetization vector is called a tunneling magneto-resistance ratio (TMR). The STT-MTJ has some advantages as follows. First, it presents non-volatility without applying any external magnetic field or electric current owing to the intrinsic characteristics of ferromagnetic materials. Second, when device size is reduced, a critical current density (JC) is also reduced. Thus, it is possible to consume lower power and to fabricate higher density. Third, fast write speed by applying sufficient current through the MTJ may be able to be available for the operation speed better than that of DRAM. From these features, a STT-MRAM is a best suitable for newly next generation memory over other nonvolatile memory devices. However, driving the STT-MRAM needs a lot of considerations which should not only accurately control the current and voltage to guarantee the data within MTJ, but also considerations which should improve the read and write operation speeds from peripheral circuits for the compatible with DRAM. In addition, there are some obstacles to overcome process variation for commercializing STT-MRAM in nanoscale era. In particular, the resistance variation of MTJ that relate to the process, voltage, and temperature (PVT) variations is serious problem to ensure a reliable memory operation. In order to estimate resistance distribution, it is necessary to investigate what factors affect MTJ properties. In this dissertation, in order to develop a core circuit of STT-MRAM such as write driver and sense amplifier, we have studied parameters affecting write and read margins from measurement and theory. We designed a reliable MTJ macro model using Verilog-A including parameter variation to perform array simulation in HSPICE. According to device shrinkage, the fabrication process has been getting difficult and complex. Therefore, unwanted or unexpected degradations of the device may cause serious errors or misoperation. In the past year, device engineers mainly took a responsibility for these problems. To solve device degradation due to PVT variation, however, a robust and tolerance design for circuit is very important in the present. Accordingly, In this dissertation, we fabricated and measured the MTJ samples with respect to process variation, and analyzed parameters from physical equation to realize its characteristics using macro model on HSPICE simulation. Then, a novel robust reading circuit, parallel reading self-reference sense amplifier (PRSA), was proposed and confirmed by postlayout simulation using proposed MTJ macro model in MRAM array. The proposed PRSA presents not only a superior readability despite of PVT variations but also faster speed than the other conventional self-reference sense amplifiers.