An Area-Efficient 10-bit Resolution Digital-to-Analog Converter for Flat-Panel Display Source Driver IC

Abstract

Recently, as the demand for vivid and realistic images increases in display applications, high-resolution source driver ICs have become essential to implement the high-color depth active matrix flat-panel displays (AMFPDs). The source driver IC is composed of several blocks such as shift-register, sampling latch, holding latch, level shifter, digital-to-analog converter (DAC), and output buffer. Among these blocks, the DAC occupies a large portion of the area of the source driver IC. Especially, since the size of the DAC exponentially increases as the resolution increases, the source driver IC with high-resolution DAC occupies a large area and thereby increases the cost. Therefore, to realize the low-cost high-resolution source driver IC, the area-efficient high-resolution DAC is necessary. In this thesis, an area-efficient high-resolution DAC using a lower 2-bit grouping method is proposed to reduce the size of the source driver IC. The proposed grouping method reduces the number of switches in the proposed DAC, and thereby the size of the source driver IC is considerably reduced. A 10-bit source driver IC with the proposed DAC is fabricated using a 0.18-μm CMOS process with 1.8 V and 18 V devices. The size of the proposed DAC is reduced by 40.6% compared with that of the conventional DAC. To verify the linearity and uniformity of the proposed DAC, the integral nonlinearity (INL), differential nonlinearity (DNL), and deviation voltage output (DVO) are measured. The measured maximum values of the INL and DNL are 0.487 LSB and 0.089 LSB, respectively. The measured maximum values of the inter-channel and inter-chip DVOs are 1.68 mV and 14.29 mV, respectively. Therefore, the proposed DAC is suitable to realize the small-sized source driver IC with high resolution.|최근에 생생하고 현실적인 디스플레이 이미지에 대한 수요가 증가함에 따라 높은 색심도의 액티브 매트릭스 평판 디스플레이(AMFPDs)를 구현하기 위한 고해상도 소스 드라이버 IC가 중요해지고 있다. 소스 드라이버 IC는 쉬프트 레지스터, 샘플링 래치, 홀딩 래치, 레벨 시프터, 디지털 아날로그 변환기(DAC), 그리고 출력 버퍼와 같이 여러 개의 블록으로 구성되어 있다. 그 블록들 중에서 DAC가 소스 드라이버 IC 면적의 상당 부분을 차지한다. 특히, DAC의 면적은 해상도가 증가할수록 급격히 증가한다. 따라서, 고해상도 DAC를 포함하는 소스 드라이버 IC는 많은 면적을 요구하며 그에 따라 소스 드라이버 IC의 가격이 증가한다. 그러므로, 값싼 고해상도 소스 드라이버 IC를 얻기 위해서는, 면적 효율이 높은 고해상도 DAC가 필요하다. 본 논문에서는, 소스 드라이버 IC의 크기를 감소시키기 위해 하위 2-bit grouping 방식을 이용한 면적 효율이 높은 고해상도 DAC를 제안하였다. 위의 grouping 방식은 제안한 DAC에 사용되는 스위치 개수를 감소시키며 그로 인해 소스 드라이버 IC의 크기가 상당히 감소된다. 제안한 DAC를 사용한 10-bit 소스 드라이버 IC는 1.8 V 와 18 V 소자를 사용하는 0.18-μm CMOS 공정을 이용해 제작되었다. 제안한 DAC의 면적은 기존의 DAC와 비교하여 40.6 %가 감소하였다. DAC의 선형성과 균일성을 검증하기 위해, 적분비선형성(INL)과 미분비선형성(DNL) 그리고 출력전압의 편차(DVO)를 측정하였다. INL과 DNL의 최대 측정치는 각각 0.487 LSB 그리고 0.089 LSB 이다. 채널간 DVO와 칩간 DVO의 최대 측정치는 각각 1.68 mV 그리고 14.29 mV 이다. 그러므로, 제안한 DAC는 소면적 고해상도 소스 드라이버 IC를 구현하기 위해 적합하다.; Recently, as the demand for vivid and realistic images increases in display applications, high-resolution source driver ICs have become essential to implement the high-color depth active matrix flat-panel displays (AMFPDs). The source driver IC is composed of several blocks such as shift-register, sampling latch, holding latch, level shifter, digital-to-analog converter (DAC), and output buffer. Among these blocks, the DAC occupies a large portion of the area of the source driver IC. Especially, since the size of the DAC exponentially increases as the resolution increases, the source driver IC with high-resolution DAC occupies a large area and thereby increases the cost. Therefore, to realize the low-cost high-resolution source driver IC, the area-efficient high-resolution DAC is necessary. In this thesis, an area-efficient high-resolution DAC using a lower 2-bit grouping method is proposed to reduce the size of the source driver IC. The proposed grouping method reduces the number of switches in the proposed DAC, and thereby the size of the source driver IC is considerably reduced. A 10-bit source driver IC with the proposed DAC is fabricated using a 0.18-μm CMOS process with 1.8 V and 18 V devices. The size of the proposed DAC is reduced by 40.6% compared with that of the conventional DAC. To verify the linearity and uniformity of the proposed DAC, the integral nonlinearity (INL), differential nonlinearity (DNL), and deviation voltage output (DVO) are measured. The measured maximum values of the INL and DNL are 0.487 LSB and 0.089 LSB, respectively. The measured maximum values of the inter-channel and inter-chip DVOs are 1.68 mV and 14.29 mV, respectively. Therefore, the proposed DAC is suitable to realize the small-sized source driver IC with high resolution.