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dc.contributor.advisorTae-Yeoul Yun-
dc.contributor.author박지예-
dc.date.accessioned2020-02-18T16:31:30Z-
dc.date.available2020-02-18T16:31:30Z-
dc.date.issued2016-02-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/126410-
dc.identifier.urihttp://hanyang.dcollection.net/common/orgView/200000428029en_US
dc.description.abstractA direct conversion receiver is a more popular architecture than a heterodyne receiver due to its low complexity, low power, and low cost chip integration. However, the direct conversion receiver suffers from a very high intrinsic flicker noise (1/f) which degrades the signal to noise ratio (SNR) and overall noise figure (NF). In this thesis, a CMOS direct down-conversion mixer with a low flicker noise is presented. A negative feedback technique is applied to the mixer using a current bleeding circuit with a resonant inductor in order to reduce flicker noise caused by a RF transconductance stage, a current bleeding circuit, a direct noise mechanism, and an indirect noise mechanism. First, the negative feedback technique reduces flicker noise generated by the RF transconductance stage and the current bleeding circuit. Second, the current bleeding technique decreasing the DC current of the LO switching stage reduces the direct switch flicker noise. Finally, the resonant inductor technique compensates for the parasitic capacitance to decrease the indirect flicker noise. The measurement results show a conversion gain of 20.6 dB at a RF input frequency of the 2.4 GHz, a third order input intercept point of -14.3 dBm, and a flicker noise of 14.2 dB at 10 kHz, which was improved by 15.6 dB compared with the current bleeding mixer. In the measurement, a RF input power was -40 dBm and a LO power was -2 dBm. The total power dissipation of the proposed mixer was 6.2 mW from a 1.2 V supply voltage. It was fabricated in a 0.11 μm CMOS process with a chip size of 0.9 × 0.85 mm2 including the pads.-
dc.publisher한양대학교-
dc.titleFlicker Noise Improved CMOS Mixer Using a Feedback Current Bleeding Technique-
dc.typeTheses-
dc.contributor.googleauthorJi-Ye Park-
dc.sector.campusS-
dc.sector.daehak대학원-
dc.sector.department전자컴퓨터통신공학과-
dc.description.degreeMaster-
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Master)
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