Wideband CMOS Low Noise Amplifiers for Wireless Communication Systems

Abstract

This dissertation deals with implementation of various wideband low-noise amplifiers (LNA), namely i) low-power LNA with common gate and current-reuse techniques, ii) low voltage-low power full-band UWB receiver front-end, and iii) analysis and optimization for resistive feedback inverter LNA. The design details of the proposed circuits are described and discussed, along with simulation and measurement results. First, Chapter 2 presents a common-gate (CG) LNA that uses the current-reuse technique and is intended to achieve both ultra-wideband and low-power consumption. The CG amplifier enables wide-band input matching with low transconductance and low frequency-independent noise figure (NF) when employed at the input stage compared with the common-source amplifier. The current-reuse technique is adopted in order to reduce the power dissipation while achieving reasonable power gain. In addition, a shunt and series peaking technique is adopted to obtain wide bandwidth. The proposed LNA achieves a 3-dB bandwidth from 2.4 to 11.2 GHz, a maximum power gain of 14.8 dB, a minimum NF of 3.9 dB and a third-order input intercept point of -11.5 dBm while consuming 3.4 mW from a 1.5 V supply. A 0.18-μm CMOS process is utilized to fabricate the LNA. Second, Chapter 3 describes a low-voltage, low-power, low-noise, wideband receiver front-end consisting of a LNA and a mixer. The LNA stage uses a current-reuse technique for low-power consumption and high gain. A switched biasing technique is then used to reduce the flicker noise of the mixer. A bulk injection structure is adopted for low-voltage operation of the mixer. The proposed receiver front-end achieves input impedance matching of less than -10 dB from 3.1 to 10.6 GHz, a minimum noise figure of 4.9 dB, and a maximum power gain of 17.7 dB while consuming 8.25 mW from 6.87 mA and 1.2 V. This receiver front-end is fabricated using a 0.18-μm CMOS process. Finally, Chapter 4 presents the analysis and optimization of a resistive-feedback inverter as a LNA for wideband applications. Conventionally, an inverter is designed with a larger PMOS than NMOS due to the mobility difference. However, a theoretical analysis demonstrates that a large-NMOS inverter provides the advantage of better power efficiency with the same performance compared to a conventional large-PMOS structure. We perform an optimization of the transistor size based on theoretical analyses by using a figure of merit that includes the voltage gain, noise figure, bandwidth, and power consumption. Measurements show a maximum power gain of 16.8 dB, a minimum noise figure of 1.84 dB, and a maximum third-order input intercept point of -9.4 dBm over 0.05 to 1.4 GHz while the LNA consumes 9.6 mW from a 1.5 V supply. The proposed LNA is implemented using a Samsung 65-nm RF CMOS process.