클럭 전달 링크를 위한 고속 유선 수신기

Abstract

이 논문은 HDMI 같이 고속으로 동작하는 클럭 전달 링크를 위한 수신기에 대한 논문이다. 수신된 데이터의 정확한 복원을 위해 클럭데이터복원 (CDR) 회로는 샘플링 클럭의 위상을 입력 데이터 eye의 중앙에 위치시킨다. CDR 회로에서, 샘플링 클럭의 위상은 위상 회전 방식의 위상동기루프 (PLL)에 의해 조절된다. CDR 회로가 최적의 샘플링 위상을 찾을 수 있도록 세 개의 탭을 가진 결정궤환등화기 (DFE)는 CTLE와 함께 케이블에 의해 생긴 loss를 보상하여 수신된 데이터의 eye를 충분히 열어준다. 데이터와 엣지의 샘플을 사용하여 adaptive하게 DFE의 계수를 계산한다. 65-nm CMOS공정으로 설계된 세 개의 채널을 가진 수신기는 디지털루프필터 (DLF)와 DFE adaptation과 같은 디지털회로까지 포함해서 0.78-mm2의 면적을 차지하며 1.2-V 전압으로부터 288-mA의 전류를 소모한다. 수신기의 측정을 위해 3-GHz에서 23-dB의 손실을 갖는 HDMI 케이블을 통해 6-Gbps의 PRBS 데이터가 입력으로 공급된다. DFE에 의해 CDR에서 복원된 샘플링 클럭의 RMS 지터가 4.1-ps 에서 2.6-ps로 개선되며 DFE의 동작 유무에 따른 지터에 대한 수신기의 tolerance를 비교 측정하였다.|This thesis presents a wireline receiver for a high-speed clock-forwarded link such as High-definition multimedia interface (HDMI). In order to correctly recover for received data, the phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three-tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous-time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65-nm CMOS process, the receiver with three-lane for a high-speed clock-forwarded link occupies 0.78-mm2 including digital logic circuits such as digital loop filter (DLF) and DFE adaptation and consumes 288-mA from a 1.2-V supply. A 6-Gbps PRBS data with 23-dB cable loss at 3-GHz is applied as input source. A RMS jitter of the sampling clocks recovered by the CDR is improved from 4.1-ps to 2.6-ps by the DFE and a tolerance of the receiver to the jitter is measured with and without DFE.; This thesis presents a wireline receiver for a high-speed clock-forwarded link such as High-definition multimedia interface (HDMI). In order to correctly recover for received data, the phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three-tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous-time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65-nm CMOS process, the receiver with three-lane for a high-speed clock-forwarded link occupies 0.78-mm2 including digital logic circuits such as digital loop filter (DLF) and DFE adaptation and consumes 288-mA from a 1.2-V supply. A 6-Gbps PRBS data with 23-dB cable loss at 3-GHz is applied as input source. A RMS jitter of the sampling clocks recovered by the CDR is improved from 4.1-ps to 2.6-ps by the DFE and a tolerance of the receiver to the jitter is measured with and without DFE.