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Multi-Stage Signal Processing Schemes for Efficient LDPC Decoding and High-Performance OFDM Radar Detection

Title
Multi-Stage Signal Processing Schemes for Efficient LDPC Decoding and High-Performance OFDM Radar Detection
Author
임진수
Alternative Author(s)
Lim, Jinsoo
Advisor(s)
신동준
Issue Date
2017-02
Publisher
한양대학교
Degree
Doctor
Abstract
This dissertation contains the following two contributions to the research topics on low-density parity-check (LDPC) codes and one contribution to orthogonal frequency division modulation (OFDM) radars: 1) Three-stage decoding scheme for systematic LDPC codes, which lowers the error floors of the LDPC codes 2) An efficient bit flipping decoding scheme for systematic LDPC codes, which reduces the power consumption with slightly increased implementation cost 3) Two-stage Doppler estimation scheme for OFDM radars, which enhances the estimation performance based on new radar signaling First, a three-stage decoding scheme using CRC is proposed to lower the error floors of systematic LDPC codes. An early stopping criterion is also proposed to avoid unnecessary decoding iterations in the first stage. If the early stopping criterion is satisfied, the first-stage decoding is stopped and the second-stage decoding is initiated, where the unsuccessfully decoded information part is redecoded based on candidate information bit flipping (CIBF) and CRC detection. If the second-stage decoding fails, the third-stage decoding is initiated by erasing log-likelihood ratio (LLR) values of the selected variable nodes. Simulation results show that the proposed scheme effectively lowers the error floors of systematic LDPC codes while reducing a decoding complexity. In the second part of this dissertation, an efficient bit flipping decoding of systematic LDPC codes is introduced. Unsuccessfully decoded codeword is efficiently re-decoded by the CIBF decoder using CRC information at the end of each iteration. We adopt the CIBF decoder to the LDPC decoding additionally and that makes it possible to reduce the power consumption because of the reduced average number of iterations and to improve the frame error rate (FER) performance. Based on the hardware cost analysis in the CMOS cell library, the additional hardware cost of the CIBF decoder is negligible compared with the conventional LDPC decoder. Finally, a two-stage Doppler estimation scheme is proposed for OFDM radar. In the presence of intercarrier interference (ICI), conventional OFDM radar exhibits serious performance degradation when estimating the Doppler frequency of a target. In order to mitigate ICI, a sequence with a good correlation property is assigned to the subcarriers to generate an OFDM signal, and oversampling is applied to the received OFDM signal in the frequency domain. Then, Doppler estimation with coarse and fine estimating steps is performed to achieve accurate Doppler estimation. Also, it is shown that the proposed scheme enables parallel calculation of correlation values to reduce the latency and enlarges the Doppler estimation range by eliminating Doppler ambiguity. Finally, simulation results are provided to show that the proposed scheme outperforms the conventional scheme with slightly increased computational complexity.
URI
https://repository.hanyang.ac.kr/handle/20.500.11754/124121http://hanyang.dcollection.net/common/orgView/200000429682
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > ELECTRONICS AND COMPUTER ENGINEERING(전자컴퓨터통신공학과) > Theses (Ph.D.)
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