Resource Efficient SRAM-based Ternary Content Addressable Memory

Abstract

Classical ternary content addressable memory (TCAM) is used to search input query string against the registered data strings in parallel. TCAM is attractive for any application that requires high-speed search operation such as search engines, network routers, virus scanning engines and so forth. Despite the attractive feature of TCAM, high power consumption per bit, high cost per bit, fixed array sizes, and complex architecture are considered as some of its critical disadvantages. To cater these shortcomings of classical TCAM, many methodologies to emulate classical TCAM using, power efficient, cost efficient, scalable, and simpler in architecture static random access memory (SRAM) have been proposed in recent times. However, these methodologies considered the throughput as the only primitive resource during the emulation of TCAM. As a result, the throughput efficient SRAM-based TCAM is emulated that reduces the SRAM utilization and the power efficiency of emulated TCAM. The goal of this thesis is to propose a novel SRAM-based TCAM memory architecture called the resource efficient SRAM-based TCAM (REST) that aid us to evaluate the efficiencies in term of its major resources -such as search-throughput, search-latency, SRAM utilization, and power consumption. In addition, REST allows selecting series of tradeoffs among resources. All of these tradeoffs are interrelated; the selection of tradeoffs is required to make for best performance under specified conditions. The REST employs the use of virtual blocks in the SRAM to enable the emulation of higher TCAM bits in its memory architecture than the one without virtual blocks. Hence, the virtual blocks efficiently utilize the SRAM and decreases the overall power consumption at the tradeoffs of added latency and reduced throughput. To evaluate the effectiveness of the REST memory Architecture for the evaluation of its resource efficiency, three different TCAMs of same size were implemented on Xilinx Kintex-7 FPGA. (I) The throughput and the latency efficient TCAM (LTE) is implemented to achieve high-performance in term of resources like latency and throughput. (II) The power and the memory efficient TCAM (PME) is implemented to achieve the high-performance in term of resources like power consumption and SRAM utilization. (III) The mid efficient TCAM is implemented to achieve the optimal performance among all resources. Results indicate that the LTE utilizes 79.3% and 96.5 % more SRAM bit resources, and consumes 45% and 55% more dynamic power than the ME and the PME respectively. However, the LTE shows an efficient single clock cycle latency and higher throughput than ME and PME, respectively. In addition to REST memory architecture, a novel logic synthesis based approach to emulate match line and comparison cell architecture of classical TCAM is proposed that can be mapped to any RAM. To prove the effectiveness of proposed technique it is mapped to SRAM. In a result of the mapping, it produces throughput and latency efficient TCAM.