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Highly Electrical Performance In-Sn-Zn-O Thin Film Transistors for Low Voltage Operation with a Zirconium Silicate Gate Dielectric Deposited by Plasma-Enhanced Atomic Layer Deposition

Title
Highly Electrical Performance In-Sn-Zn-O Thin Film Transistors for Low Voltage Operation with a Zirconium Silicate Gate Dielectric Deposited by Plasma-Enhanced Atomic Layer Deposition
Author
김민정
Alternative Author(s)
김민정
Advisor(s)
박진성
Issue Date
2020-02
Publisher
한양대학교
Degree
Master
Abstract
In this study, zirconium silicate (Zr silicate) film was successfully fabricated by plasma enhanced atomic layer deposition (PEALD) process with cycle ratio 1 : 1 = ZrO2 : SiO2. Zr silicate thin film has advantages of SiO2 and ZrO2 thin films, such as low leakage current, amorphous state and smooth interface. We also fabricated indium-tin-zinc oxide (ITZO) thin film transistors (TFTs) using 3 different gate dielectric : SiO2, ZrO2 and Zr silicate, respectively. ZrO2 TFTs show poor electrical performance (field-effect mobility, μsat: 16.2 cm2/Vs and subthreshold swing, SS: 0.20 V/decade) compare to SiO2 TFTs despite of high dielectric constant (ZrO2: 25 and SiO2: 3.8). Highly crystalline, rough surface of thin films and coulomb scattering dominant mobility degradation made TFTs degraded. However, Zr silicate TFTs show high electrical performance (μsat: 28.6 cm2/Vs and SS: 0.15 V/decade) due to smooth surface and moderate high dielectric constant (8.4). Device instabilities (positive bias temperature stress, PBTS and negative bias temperature stress, NBTS) of 3 different gate dielectric were also measured. Oxygen-rich of ZrO2 TFTs show poor PBTS and oxygen-poor of SiO2 TFTs show poor NBTS characteristics. However, Zr silicate TFTs improved device instabilities. Consequently, Zr silicate gate dielectrics are candidate materials for high electrical performance, device instability and low-voltage operation.
URI
https://repository.hanyang.ac.kr/handle/20.500.11754/123299http://hanyang.dcollection.net/common/orgView/200000436893
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Master)
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