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dc.contributor.author유봉영-
dc.date.accessioned2020-01-20T07:45:32Z-
dc.date.available2020-01-20T07:45:32Z-
dc.date.issued2019-10-
dc.identifier.citationJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 19, No. 10, Page. 6512-6515en_US
dc.identifier.issn1533-4880-
dc.identifier.issn1533-4899-
dc.identifier.urihttps://www.ingentaconnect.com/contentone/asp/jnn/2019/00000019/00000010/art00088-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/122113-
dc.description.abstractCu overburden layers on the trenches from redistribution layer process of fan-out wafer level packaging were successfully polished by electrochemical polishing method. For the uniform electrochemical polishing of Cu overburden on inside and outside of the trenches, thickness of the Cu overburden was controlled to have same thickness at the both side of trenches by addition of the additives such as accelerator, suppressor, and leveler. Before the electrochemical polishing of Cu overburden, optimum polishing potential and polishing rates were determined to 1.3 V and 462 nm/C.cm(-2) through the cyclic voltammetry analysis and observation of electrochemical polishing behavior of Cu planar substrate in 85% H3PO4. Electrochemical polishing of Cu overburden was carried out at the condition determined from the previous experiment. The results of electrochemical polishing indicated that Cu overburden on both side of trenches was totally removed simultaneously at the end of electrochemical polishing and Cu overburden profile was important for the uniform planarization of Cu overburden on both side of the trenches.en_US
dc.description.sponsorshipThis work was supported by the MOTIE (Ministry of Trade, Industry and Energy) (No. 10048778) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device, the MOTIE (No. 10067804) and KSRC support program for the development of the future semiconductor device, and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (No. 2015R1A5A1037548).en_US
dc.language.isoen_USen_US
dc.publisherAMER SCIENTIFIC PUBLISHERSen_US
dc.subjectFOWLPen_US
dc.subjectElectrochemical Polishingen_US
dc.subjectElectropolishingen_US
dc.subjectECPen_US
dc.subjectTrench Fillingen_US
dc.titleElectrochemical Polishing of Cu Redistribution Layers for Fan-Out Wafer Level Packagingen_US
dc.typeArticleen_US
dc.relation.no10-
dc.relation.volume19-
dc.identifier.doi10.1166/jnn.2019.17061-
dc.relation.page6512-6515-
dc.relation.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY-
dc.contributor.googleauthorPark, Kimoon-
dc.contributor.googleauthorLee, Jinhyun-
dc.contributor.googleauthorYoo, Bongyoung-
dc.relation.code2019037685-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDEPARTMENT OF MATERIALS SCIENCE AND CHEMICAL ENGINEERING-
dc.identifier.pidbyyoo-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > MATERIALS SCIENCE AND CHEMICAL ENGINEERING(재료화학공학과) > Articles
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