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DRBAC: Dynamic Row Buffer Access Control for Power and Performance of DRAM Systems

Title
DRBAC: Dynamic Row Buffer Access Control for Power and Performance of DRAM Systems
Author
정기석
Keywords
memory controller; memory scheduling; energy-aware system
Issue Date
2018-06
Publisher
IEEK PUBLICATION CENTER
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 18, no. 3, page. 307-314
Abstract
Performance of dynamic random access memory (DRAM) has been steadily improved to overcome the concern that the DRAM access time may become the performance bottleneck of a system. Besides, DRAM power consumption has become a critical issue in mobile and server systems. The open page policy is widely used to minimize the memory access latency and the power consumption of the activate and the precharge commands. In this paper, we analyze DRAM power and performance according to memory request characteristics of applications. Especially, we observe that the row buffer access control influences the overall performance and power consumption. Further, the power-delay product (PDP) is sensitive to the row buffer hit ratio and the memory request frequency. Thus, we propose a method called dynamic row buffer access control (DRBAC) that changes the row buffer access limit dynamically based on the memory request characteristics. From simulation results, it is verified that DRBAC reduces the PDP value by up to 17.8% compared to the conventional method for various benchmarks. Therefore, we conclude that the proposed DRBAC is very effective for low power and high performance DRAM systems.
URI
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07469316&language=ko_KRhttps://repository.hanyang.ac.kr/handle/20.500.11754/119181
ISSN
1598-1657; 2233-4866
DOI
10.5573/JSTS.2018.18.3.307
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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