Duty-cycle and phase spacing error correction circuit for high-speed serial link

Abstract

Duty cycle and phase spacing of multi-phase clock are converted to an analog voltage by low-pass filtering a clock pulse and quantized by a low-power analog-to-digital converter (ADC). The pull-up and pull-down strengths and the delay of clock buffer are controlled till the duty cycle and phase spacing measured by the ADC become equal to desired values. A prototype has been implemented in a 28-nm CMOS process for a 12-Gbps serial link transceiver and occupies only 0.0014-mm(2). Experimental results show the deterministic jitter decreases from 8.12-ps to 0.91-ps by the proposed duty cycle and phase spacing error correction technique. While operating with a 1.0-V supply, the additional power consumed for the duty cycle and phase spacing error correction is only 76-mu W.