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Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems

Title
Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems
Author
박영준
Keywords
memory; DRAM; NVM; hybrid; cache; bandwidth
Issue Date
2017-06
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE ELECTRONICS EXPRESS, v. 14, no. 11, Article no. 20170437
Abstract
Satisfying a demand for higher memory capacity is a major problem for computing systems. Conventional solutions are reaching those limits; instead, DRAM/NVM hybrid main memory systems which consist of emerging Non-Volatile Memory for large capacity and DRAM last-level cache for high access speed were proposed for further improvement. However, in these systems, the two device types share limited memory channels/ranks and NVM channels/ranks are often less utilized than DRAM ones. This paper proposes an OBYST (On hit BYpass to STeal bandwidth) technique to improve memory bandwidth by selectively sending read requests that hit on DRAM cache to NVM instead of busy DRAM. We also propose an inter-device request scheduling policy optimized to OBYST. With negligible area overhead, OBYST improves bandwidth, IPC, and EDP by up to 22%, 21%, and 26% over the baseline without bandwidth optimizations, respectively.
URI
https://www.jstage.jst.go.jp/article/elex/14/11/14_14.20170437/_articlehttps://repository.hanyang.ac.kr/handle/20.500.11754/114487
ISSN
1349-2543
DOI
10.1587/elex.14.20170437
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE(컴퓨터소프트웨어학부) > Articles
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