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Fast compact true random number generator based on multiple sampling

Title
Fast compact true random number generator based on multiple sampling
Author
김동규
Keywords
content-addressable storage; random-access storage; CMOS digital integrated circuits; 3T-2R nvTCAM; nonvolatile ternary content-addressable-memory; voltage limiter; self-controlled bias circuit; match line development; sensing margin; resistance ratio; sensing delay; CMOS process; size 65 nm
Issue Date
2017-06
Publisher
INST ENGINEERING TECHNOLOGY-IET
Citation
ELECTRONICS LETTERS, v. 53, no. 13, page. 841-842
Abstract
A new ring-oscillator-based true random number generator (RNG) based on multiple sampling is proposed. The proposed generator uses the outputs of all gates in a ring oscillator, as positive-and negative-edge clock signals. The generator in two field-programmable gate array families is implemented, and it is verified that the generated bit sequences pass the RNG tests of the National Institute of Standards and Technology. The experimental results show that the proposed generator is faster and more compact than the existing ring-oscillator-based true RNGs.
URI
https://digital-library.theiet.org/content/journals/10.1049/el.2017.1202https://repository.hanyang.ac.kr/handle/20.500.11754/114371
ISSN
0013-5194; 1350-911X
DOI
10.1049/el.2017.1202
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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