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dc.contributor.author송윤흡-
dc.date.accessioned2019-11-25T06:18:29Z-
dc.date.available2019-11-25T06:18:29Z-
dc.date.issued2017-05-
dc.identifier.citationNANOSCIENCE AND NANOTECHNOLOGY LETTERS, v. 9, no. 5, page. 736-740en_US
dc.identifier.issn1941-4900-
dc.identifier.issn1941-4919-
dc.identifier.urihttps://www.ingentaconnect.com/content/asp/nnl/2017/00000009/00000005/art00018-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/114163-
dc.description.abstractThe cell characteristics of a vertically stacked NAND (V-NAND) flash memory with a poly-GaAs channel are investigated for the effect of grain using a three-dimensional simulation method, and they are compared to V-NAND with a poly-silicon channel. Under the same physical conditions, it is confirmed that the initial status of the V-NAND flash memory with a poly-GaAs channel shows a higher drain current and higher threshold voltage, which provides a better feasibility to improve the V-NAND flash memory. Due to the grain, V-NAND flash memory with a poly-GaAs channel shows more degradation in cell characteristics as the grain length decreases and the trap density in the grain boundary increases, compared to the V-NAND with a poly-silicon channel. Here, we explain that the higher energy band diagram in the poly-GaAs channel causes these results. The values of the trap density and grain length in the poly-GaAs channel are very important; the trap density should be maintained at a value less than 9e-13 cm(-2)eV(-1) and the grain length should be maintained at a value more than 50 nm in order to obtain better cell characteristics compared to the V-NAND with a poly-Si channel.en_US
dc.description.sponsorshipThis research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT and Future Planning (NRF-2016M3A7B4910398). We especially thank Dr. Jaegoo Lee and Dr. Jaehoon Jang at Memory R&D Center, Memory Division, Samsung Electronics Co. Ltd., for their technical advice and comments on this study.en_US
dc.language.isoen_USen_US
dc.publisherAMER SCIENTIFIC PUBLISHERSen_US
dc.subject3D NAND Flash Memoryen_US
dc.subjectGaAs Channelen_US
dc.subjectGrain Boundaryen_US
dc.subjectTCAD Simulationen_US
dc.titleInvestigation of the Effect of Grain for Vertically Stacked NAND Flash Memory with a Poly-GaAs Channelen_US
dc.typeArticleen_US
dc.relation.no5-
dc.relation.volume9-
dc.identifier.doi10.1166/nnl.2017.2381-
dc.relation.page736-740-
dc.relation.journalNANOSCIENCE AND NANOTECHNOLOGY LETTERS-
dc.contributor.googleauthorOh, Young-Taek-
dc.contributor.googleauthorShin, Sang-Hoon-
dc.contributor.googleauthorKim, Kyu-Beom-
dc.contributor.googleauthorSong, Yun-Heub-
dc.relation.code2017006335-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidyhsong2008-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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