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Investigation of the Effect of Grain for Vertically Stacked NAND Flash Memory with a Poly-GaAs Channel

Title
Investigation of the Effect of Grain for Vertically Stacked NAND Flash Memory with a Poly-GaAs Channel
Author
송윤흡
Keywords
3D NAND Flash Memory; GaAs Channel; Grain Boundary; TCAD Simulation
Issue Date
2017-05
Publisher
AMER SCIENTIFIC PUBLISHERS
Citation
NANOSCIENCE AND NANOTECHNOLOGY LETTERS, v. 9, no. 5, page. 736-740
Abstract
The cell characteristics of a vertically stacked NAND (V-NAND) flash memory with a poly-GaAs channel are investigated for the effect of grain using a three-dimensional simulation method, and they are compared to V-NAND with a poly-silicon channel. Under the same physical conditions, it is confirmed that the initial status of the V-NAND flash memory with a poly-GaAs channel shows a higher drain current and higher threshold voltage, which provides a better feasibility to improve the V-NAND flash memory. Due to the grain, V-NAND flash memory with a poly-GaAs channel shows more degradation in cell characteristics as the grain length decreases and the trap density in the grain boundary increases, compared to the V-NAND with a poly-silicon channel. Here, we explain that the higher energy band diagram in the poly-GaAs channel causes these results. The values of the trap density and grain length in the poly-GaAs channel are very important; the trap density should be maintained at a value less than 9e-13 cm(-2)eV(-1) and the grain length should be maintained at a value more than 50 nm in order to obtain better cell characteristics compared to the V-NAND with a poly-Si channel.
URI
https://www.ingentaconnect.com/content/asp/nnl/2017/00000009/00000005/art00018https://repository.hanyang.ac.kr/handle/20.500.11754/114163
ISSN
1941-4900; 1941-4919
DOI
10.1166/nnl.2017.2381
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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