Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 전형탁 | - |
dc.date.accessioned | 2019-11-20T08:36:30Z | - |
dc.date.available | 2019-11-20T08:36:30Z | - |
dc.date.issued | 2017-02 | - |
dc.identifier.citation | AIP ADVANCES, v. 7, no. 2, Article no. 025311 | en_US |
dc.identifier.issn | 2158-3226 | - |
dc.identifier.uri | https://aip.scitation.org/doi/10.1063/1.4977887 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/112648 | - |
dc.description.abstract | We report the effect of zirconium oxide (ZrO2) layers on the electrical characteristics of multilayered tin disulfide (SnS2) formed by atomic layer deposition (ALD) at low temperatures. SnS2 is a two-dimensional (2D) layered material which exhibits a promising electrical characteristics as a channel material for field-effect transistors (FETs) because of its high mobility, good on/off ratio and low temperature processability. In order to apply these 2D materials to large-scale and flexible electronics, it is essential to develop processes that are compatible with current electronic device manufacturing technology which should be conducted at low temperatures. Here, we deposited a crystalline SnS2 at 150 degrees C using ALD, and we then annealed at 300 degrees C. X-ray diffraction (XRD) and Raman spectroscopy measurements before and after the annealing showed that SnS2 had a hexagonal (001) peak at 14.9 degrees and A(1g) mode at 313 cm(-1). The annealed SnS2 exhibited clearly a layered structure confirmed by the high resolution transmission electron microscope (HRTEM) images. Back-gate FETs with SnS2 channel sandwiched by top and bottom ZrO2 on p(++) Si/SiO2 substrate were suggested to improve electrical characteristics. We used a bottom ZrO2 layer to increase adhesion between the channel and the substrate and a top ZrO2 layer to improve contact property, passivate surface, and protect from process-induced damages to the channel. ZTZ (ZrO2/SnS2/ZrO2) FETs showed improved electrical characteristics with an on/off ratio of from 0.39 x10(3) to 6.39 x10(3) and a mobility of from 0.0076 cm(2)/ Vs to 0.06 cm(2)/Vs. (c) 2017 Author(s). | en_US |
dc.description.sponsorship | This study was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (MEST) (NRF-2014M3A7B4049367). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER INST PHYSICS | en_US |
dc.subject | TRANSITION-METAL DICHALCOGENIDES | en_US |
dc.subject | FIELD-EFFECT TRANSISTORS | en_US |
dc.subject | MOS2 TRANSISTORS | en_US |
dc.subject | MONOLAYER | en_US |
dc.subject | GRAPHENE | en_US |
dc.subject | SNS2 | en_US |
dc.title | Improved electrical properties of atomic layer deposited tin disulfide at low temperatures using ZrO2 layer | en_US |
dc.type | Article | en_US |
dc.relation.no | 2 | - |
dc.relation.volume | 7 | - |
dc.identifier.doi | 10.1063/1.4977887 | - |
dc.relation.page | 1-6 | - |
dc.relation.journal | AIP ADVANCES | - |
dc.contributor.googleauthor | Lee, Juhyun | - |
dc.contributor.googleauthor | Lee, Jeongsu | - |
dc.contributor.googleauthor | Ham, Giyul | - |
dc.contributor.googleauthor | Shin, Seokyoon | - |
dc.contributor.googleauthor | Park, Joohyun | - |
dc.contributor.googleauthor | Choi, Hyeongsu | - |
dc.contributor.googleauthor | Lee, Seungjin | - |
dc.contributor.googleauthor | Kim, Juyoung | - |
dc.contributor.googleauthor | Sul, Onejae | - |
dc.contributor.googleauthor | Jeon, Hyeongtag | - |
dc.relation.code | 2017010714 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF MATERIALS SCIENCE AND ENGINEERING | - |
dc.identifier.pid | hjeon | - |
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