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dc.contributor.author정기석-
dc.date.accessioned2019-11-19T05:54:39Z-
dc.date.available2019-11-19T05:54:39Z-
dc.date.issued2017-01-
dc.identifier.citationIEEE COMPUTER ARCHITECTURE LETTERS, v. 16, no. 1, page. 10-13en_US
dc.identifier.issn1556-6056-
dc.identifier.issn1556-6064-
dc.identifier.urihttps://ieeexplore.ieee.org/document/7544479-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/112328-
dc.description.abstract3D-stacked DRAM has been actively studied to overcome the limits of conventional DRAM. The Hybrid Memory Cube (HMC) is a type of 3D-stacked DRAM that has drawn great attention because of its usability for server systems and processing-in-memory (PIM) architecture. Since HMC is not directly stacked on the processor die where the central processing units (CPUs) and graphic processing units (GPUs) are integrated, HMC has to be linked to other processor components through high speed serial links. Therefore, the communication bandwidth and latency should be carefully estimated to evaluate the performance of HMC. However, most existing HMC simulators employ only simple HMC modeling. In this paper, we propose a cycle-accurate simulator for hybrid memory cube called CasHMC. It provides a cycle-by-cycle simulation of every module in an HMC and generates analysis results including a bandwidth graph and statistical data. Furthermore, CasHMC is implemented in C++ as a single wrapped object that includes an HMC controller, communication links, and HMC memory. Instantiating this single wrapped object facilitates simultaneous simulation in parallel with other simulators that generate memory access patterns such as a processor simulator or a memory trace generator.en_US
dc.description.sponsorshipThis work was supported by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (R7119-16-1009, Development of Intelligent Semiconductor Core Technologies for IoT Devices based on Harvest Energy). Ki-Seok Chung is the corresponding author.en_US
dc.language.isoenen_US
dc.publisherIEEE COMPUTER SOCen_US
dc.subjectMemory control and accessen_US
dc.subjectmemory designen_US
dc.subjectmodeling of computer architectureen_US
dc.subjectsimulationen_US
dc.titleCasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cubeen_US
dc.typeArticleen_US
dc.relation.no1-
dc.relation.volume16-
dc.identifier.doi10.1109/LCA.2016.2600601-
dc.relation.page10-13-
dc.relation.journalIEEE COMPUTER ARCHITECTURE LETTERS-
dc.contributor.googleauthorJeon, Dong-Ik-
dc.contributor.googleauthorChung, Ki-Seok-
dc.relation.code2017008355-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidkchung-
dc.identifier.orcidhttp://orcid.org/0000-0002-2908-8443-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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