Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 강창욱 | - |
dc.date.accessioned | 2019-09-26T01:54:10Z | - |
dc.date.available | 2019-09-26T01:54:10Z | - |
dc.date.issued | 2005-05 | - |
dc.identifier.citation | 한국산업경영시스템학회 2005 춘계학술대회 논문집, Page. 111-115 | en_US |
dc.identifier.uri | http://db.koreascholar.com/Article?code=354128 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/110668 | - |
dc.description.abstract | The need for accurate yield prediction is increasing for estimating productivity and production costs to secure high revenues in the semiconductor industry. Corresponding to this end, we introduce new spatial modeling approaches for spatially clustered defects on an integrated circuit (IC) wafer map. We use spatial location of an IC chip on the wafer as a covariate on corresponding defects count listed in a wafer map. Analysis results indicate that yield prediction can be greatly improved by capturing spatial features of defects. Tyagi and Bayoumi's (1994) wafer map data are used to illustrate the procedure. | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 한국산업경영시스템학회 | en_US |
dc.subject | Integrated Circuits (ICs) | en_US |
dc.subject | Spatial clustering | en_US |
dc.subject | Zero-inflated Poisson (ZIP) regression | en_US |
dc.subject | Yield | en_US |
dc.title | A Modeling Approach of Spatially Distributed Defects in a Semiconductor Manufacturing | en_US |
dc.type | Article | en_US |
dc.contributor.googleauthor | Bae, Suk Joo | - |
dc.contributor.googleauthor | Jeong, In-Jae | - |
dc.contributor.googleauthor | Kang, Chang Wook | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DEPARTMENT OF INDUSTRIAL AND MANAGEMENT ENGINEERING | - |
dc.identifier.pid | cwkang57 | - |
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