260 0

Full metadata record

DC FieldValueLanguage
dc.contributor.author강창욱-
dc.date.accessioned2019-09-26T01:54:10Z-
dc.date.available2019-09-26T01:54:10Z-
dc.date.issued2005-05-
dc.identifier.citation한국산업경영시스템학회 2005 춘계학술대회 논문집, Page. 111-115en_US
dc.identifier.urihttp://db.koreascholar.com/Article?code=354128-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/110668-
dc.description.abstractThe need for accurate yield prediction is increasing for estimating productivity and production costs to secure high revenues in the semiconductor industry. Corresponding to this end, we introduce new spatial modeling approaches for spatially clustered defects on an integrated circuit (IC) wafer map. We use spatial location of an IC chip on the wafer as a covariate on corresponding defects count listed in a wafer map. Analysis results indicate that yield prediction can be greatly improved by capturing spatial features of defects. Tyagi and Bayoumi's (1994) wafer map data are used to illustrate the procedure.en_US
dc.language.isoko_KRen_US
dc.publisher한국산업경영시스템학회en_US
dc.subjectIntegrated Circuits (ICs)en_US
dc.subjectSpatial clusteringen_US
dc.subjectZero-inflated Poisson (ZIP) regressionen_US
dc.subjectYielden_US
dc.titleA Modeling Approach of Spatially Distributed Defects in a Semiconductor Manufacturingen_US
dc.typeArticleen_US
dc.contributor.googleauthorBae, Suk Joo-
dc.contributor.googleauthorJeong, In-Jae-
dc.contributor.googleauthorKang, Chang Wook-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDEPARTMENT OF INDUSTRIAL AND MANAGEMENT ENGINEERING-
dc.identifier.pidcwkang57-
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > INDUSTRIAL AND MANAGEMENT ENGINEERING(산업경영공학과) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE