694 0

Cost Effective Test Planning for System-on-Chip Manufacture

Title
Cost Effective Test Planning for System-on-Chip Manufacture
Author
이성준
Issue Date
2006-09
Publisher
IEEE
Citation
2006 IEEE Autotestcon, Page. 86-92
Abstract
The test of chip has become an important issue as its complexity has been dramatically increased. Currently, system-on-chip (SoC) is major product that can be used for many applications. Since the SoC is a chip designed by VLSI design techniques, its methodologies of design and test are similar to conventional chip manufacturing aspects. However, the complexity, developing procedures, and many other things are different from the case of the conventional chips. Thus, new test approach is needed for complex SoC. The proposed economics model for SoC helps the chip developers predict total cost of SoC development at the early design stage, and decide the strategy to test by cost-effective way.
URI
https://ieeexplore.ieee.org/document/4062340https://repository.hanyang.ac.kr/handle/20.500.11754/108500
ISSN
1088-7725; 1558-4550
DOI
10.1109/AUTEST.2006.283605
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > INTEGRATIVE ENGINEERING(융합공학과) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE