Repository at Hanyang UniversityCOLLEGE OF ENGINEERING SCIENCES[E](공학대학)ELECTRICAL ENGINEERING(전자공학부)Articles
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0.35um CMOS 공정을 이용한 새로운 위상고정 시간이 빠른 위상고정 루프
- Title
- 0.35um CMOS 공정을 이용한 새로운 위상고정 시간이 빠른 위상고정 루프
- Other Titles
- A New Fast Locking Time Phase-Locked Loop Using Standard 0.35㎛ CMOS Process Parameter
- Author
- 김희준
- Issue Date
- 2007-11
- Publisher
- 대한전자공학회
- Citation
- 대한전자공학회 2007년도 추계학술대회 논문집Ⅱ, Page. 655 - 656
- Abstract
- This paper presents a new fast locking phase-locked loop. Although the conventional fast phase-locked loop has two tuning loops, a proposed phase-locked loop was realized using just one tuning loop. The proposed circuit was simulated by HSPICE with a standard CMOS 0.35㎛ process parameter.
- URI
- http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE06324951&language=ko_KRhttps://repository.hanyang.ac.kr/handle/20.500.11754/107250
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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