DFD를 위한 효율적인 콤플렉스 셀 설계

Abstract

In this paper, we propose complex gate type structures, for design for debug and repair. When an error is found on a semiconductor chip, we want to fix the error by using the spare cells. Our complex gates based spare cells use 55% less NMOSs and PMOSs on the average, when compared to standard cell NAND gate structures, for ISCAS85 benchmark circuits.