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A Simulation Study on Electron Mobility of Nano-Scale SOI and Strained Si SGOI n-MOSFET Using Relaxation Time Approximation Method;12008-02\ՑYPxhttps://repository.hanyang.ac.kr/handle/20.500.11754/148026;
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t\ complementary-metal-oxide-semiconductor(CMOS)FETX 8D tհX0 t lpx , \ < \ l t \ ɉ . t\ l Ŕ X ٳ % \| ̹ܴp 买 Ǭ\ SOI(Silicon On Insulator) . SOI lpȔ C-MOSFETX 8x X(latch-up) D lp<\ )` . \ 81 U (threshold voltage) tXX 81 00(sub-threshold slope)| ¤Д 1D D . п̹ DȲ| @ ҜU4Ѥ (transconductance)| . t\ SOIlpX ǔ ̹D @ DȲ. SOI lpX <\ FBE(Floating Body Effect) . tǃ@ t Tɹ5 И t. FBE\ xX 81Ut X, DX ȐǍĳ X kink effect| XՔ 8t . t@ @ 8| tհX0 t FD SOI(Fully-Depletion SOI)lp l . FD SOI lpȔ /ܴxX i Jt ¬X 5 @ lpt.
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strained SGOI n-MOSFET \ Ȑ tٳĳ Si5 Tɹ5 t SiGe5D 1 biaxial tensile ¸x Xt ¤Д \ l t T. ҈ Ȑ tٳĳ ¸x Xt band splitting п̹ DȲ| 4-fold valleyX (t X0 L8 intervalley | t .
FD C-MOSFETX D 8t 60nm T D 0|, lpȔ 20nm T @ Pخx ultra thin body SOI C-MOSFET Si5t 10nm T Dĳ] lX . surface roughness scattering@ Ȑ tٳĳ PܴɌ ƥD |\. Si5X Pخ h 0| Ȑ tٳĳ @ X Ĭ | t ǩXՔ t @ X Ĭ surface roughness scatteringt ǩ\.
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l 4ܴ tD, 2-fold@ 4-fold valleyX electron population, intra-, intervalley | , surface roughness scattering @ Ȑ XX 20nm tXX SOI@ strained SGOI n-MOSFET x |X Si5 Pخ Xt1D l. Ĭ@ RTA(Relaxation Time Approximation) )D X.; There have been many reports about that the electron mobility for strained SGOI (strained Si/relaxed SiGe/SiO2/Si) n-MOSFET is enhanced by biaxial tensile strain induced by an inserted SiGe layer between top silicon and buried oxide layer. In particular the electron mobility is enhanced by the suppression of intervalley phonon scattering due to the strain-induced band splitting as well as the decrease in the occupancy of the 4-fold valleys.
As the channel length of fully depleted C-MOSFET becomes less than 60nm, the device structure requires the ultra thin body silicon on insulator C-MOSFET thickness of less than 20nm, the top silicon becomes less than 10nm, the surface roughness scattering affects to the electron mobility significantly.
Decrease in electron mobility as top silicon thickness reduced is attributed to mainly the phonon scattering at the low electric field region, while to the surface roughness scattering at the high electric field region.
However, since most of researchers have studied only strain Si in a viewpoint of phonon scattering, the effect of surface roughness scattering on the current transport of strained SGOI n-MOSFET with strained Si thickness of less than 10nm has been overlooked.
In our study, thus we investigated nano scale Si thickness dependency of electron mobility in SOI and strained SGOI n-MOSFET below 20nm via estimating electronic states such as energy band diagr<am, electron population in 2-fold and 4-fold valleys, intra- and intervalley phonon scattering, and surface roughness scattering.&HQsj&)KLng9 B)K,N=_Jl=_
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