Browsing byAuthor백상현

Jump to:
All A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
  • Sort by:
  • In order:
  • Results/Page
  • Authors/Record:

Showing results 1 to 30 of 43

Issue DateTitleAuthor(s)
2016-09A 65 nm Temporally Hardened Flip-Flop Circuit백상현
2017-02Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM백상현
2017-02An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation백상현
2005-03Analytical Test Buffer Design For Differential Signaling I/O Buffers by Error Syndrome Analysis백상현
2019-06Architectural design tradeoffs in SRAM-based TCAMs백상현
2016-11An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology백상현
2016-10Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation백상현
2017-07BPPT–Bulk Potential Protection Technique for Hardened Sequentials백상현
2005-09Built-In Null Detector Design For AC-Coupled Differential Receive Buffer백상현
2019-08Correctable and uncorrectable errors using large scale DRAM DIMMs in replacement network servers백상현
2007-12Delay Fault Coverage Enhancement by Partial Clocking For Low Power Designs with Heavily Gated Clocks백상현
2006-11Efficient Interconnect Test Patterns for Crosstalk and Static Faults백상현
2020-05Energy straggling and an experimental investigation of Bragg's rule for Am-241 alpha particles in air and its constituents백상현
2017-01Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs백상현
2019-08Experimental Exploitation of Random and Deterministic Data Patterns for Stringent DDR4 I/O Timing Margins백상현
2016-02Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 x nm technology백상현
2021-10Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation백상현
2020-10Failure Analysis of Galaxy S7 Edge Smartphone Using Neutron Radiation백상현
2018-09Failure signature analysis of power-opens in DDR3 SDRAMs백상현
2021-09Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics백상현
2020-07FBGA solder ball defect e ff ect on DDR4 data signal rise time and ISI measured by loading the data line with a capacitor백상현
2008-12Hysteresis 버퍼를 이용한 AC 커플링 커패시터 테스트백상현
2008-03Low Power Configuration Strategy of TCAM Lookup백상현
2008-07Low Power Ternary Content-Addressable Memories (TCAM) Design Using Segmented Match-Line백상현
2018-08Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree백상현
2017-05A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience백상현
2019-09Radiation Reliability Benefit of Area-Optimized Interleaved Flip-Flop Layout in 28 nm Technology백상현
2004-10Removing JTAG Bottleneck in System Interconnect Test백상현
2017-04Resource-Efficient SRAM-Based Ternary Content Addressable Memory백상현
2008-09Ring Oscillator를 이용한 신호의 동시 스위칭 밀도 분석백상현